CS4210 Datasheet, PDF (40/102 Pages) National Semiconductor (TI) – IEEE 1394 OHCI Controller

Register Descriptions (Continued)
4.3 PCI CONFIGURATION REGISTERS
The PCI configuration space for the CS4210 is header type
0. Header type 0 is the format for the device’s configuration
header region which is the first 16 DWORDs of PCI config-
uration space. The configuration and operational registers
are memory mapped into PCI memory address space and
pointed to by Base Address Registers (BARs) in the PCI
configuration space. PCI configuration space is not directly
memory or I/O mapped - its access is system dependent. A
software reset issued through the HCControl register does
not affect the contents of the PCI configuration space.
Table 4-5 is a map for the PCI Configuration Registers.
Table 4-6 gives detailed bit information.
Table 4-5. PCI Configuration Register Map: Index xxh
Bits
Index 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00h-
03h
04h-
07h
Device Identification Register
Device ID
Status Register
devsel
Timing
RSVD
Vendor Identification Register
Vendor ID
Command Register
RSVD
08h-
0Bh
0Ch-
0Fh
10h-
13h
Base Class
PCI BIST Register
BIST
PCI Device Class Code
Revision ID
Sub Class
Programming Interface
revisionID
PCI Header Type
PCI Latency Timer
Register
PCI Cache Line Size
Register
Header Type
latencyTimer
cacheLineSize
Base Address Register 0 - OHCI Configuration Registers
Base Address 0
RSVD
TP
14h-
17h
Base Address Register 1 - National Specific Configuration Registers
Base Address 0
RSVD
TP
18h-
2Bh
2Ch-
2Fh
30h-
33h
34h-
37h
38h-
3Bh
3Ch-
3Fh
40h-
43h
Subsystem ID
Subsystem ID
Reserved
RSVD
Max Latency
Max Latency
Min Grant
Min Grant
Reserved
Reserved
Subsystem Vendor ID
Subsys Vend ID
Reserved
Capabilities
Capabilities Pointer
Reserved
Interrupt Pin
Interrupt Pin
Interrupt Line
Interrupt Line
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