CS4210 Datasheet, PDF (12/102 Pages) National Semiconductor (TI) – IEEE 1394 OHCI Controller

Signal Definitions (Continued)
2.2 SIGNAL DESCRIPTIONS
2.2.1 PCI Bus Interface Signals
Signal Name
Pin No.
Type
AD[31:0]
Refer to
I/O
Table 2-3
C/BE[3:0]#
FRAME#
IRDY#
65, 53, 41,
I/O
28
43
I/O
44
I/O
TRDY#
45
I/O
STOP#
48
I/O
DEVSEL#
47
I/O
IDSEL
PERR#
29
I
49
I/O
SERR#
51
I/O
PAR
PREQ#
PGNT#
INTA#
52
I/O
15
O
14
I
8
O
Description
Multiplexed Address and Data
AD[31:0] is a physical address during the first clock of a PCI transaction; it is
the data during subsequent clocks.
When the CS4210 is a PCI master, AD[31:0] are outputs during the address
and write data phases, and are inputs during the read data phase of a trans-
action.
When the CS4210 is a PCI slave, AD[31:0] are inputs during the address
and write data phases, and are outputs during the read data phase of a
transaction.
Bus Command and Byte Enables
Multiplexed bus command and byte enables.
Cycle Frame
Driven by the initiator to indicate the beginning and duration of an access.
Initiator Ready
Indicates that the initiator is ready to complete the current data phase of the
transaction.
Target Ready
Indicates that the current data phase of the transaction is ready to be com-
pleted.
Stop
Indicates that the current target is requesting the initiator to stop the current
transaction.
Device Select
When actively driven, DEVSEL# indicates the driving device has decoded
its address as the target of the current access.
Initialization Device Select
Used as a chip select during configuration read and write transactions.
Parity Error
Used for reporting data parity errors during all PCI transactions except a
Special Cycle.
System Error
Used for reporting address parity errors, data parity errors on the Special
Cycle command, or any other system error where the result will be cata-
strophic.
Parity
PAR is even parity across AD[31:0] and C/BE[3:0]. PAR is an input when
AD[31:0] are inputs and is an output when AD[31:0] are outputs.
PCI Bus Request
PCI bus request to PCI bus arbiter.
PCI Bus Grant
PCI bus grant from PCI bus arbiter.
Interrupt A
1394 OpenHCI PCI interrupt.
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