CS4210 Datasheet, PDF (43/102 Pages) National Semiconductor (TI) – IEEE 1394 OHCI Controller

Register Descriptions (Continued)
Table 4-6. PCI Configuration Register Definitions
Bit
Name
Access Reset Description
Index 06h
PCI Status Register
15
detectedParErr
R/W
14
signalSysErr
R/W
13
recvMasterAbort
R/W
12
recvTargeAbort
R/W
11
signalTargetAbort
R/W
10:9
devselTiming
RO
8
dataParityRep
R/W
7:0
RSVD
RO
0
Detected Parity Error: This bit is set whenever a parity error is detected.
Write 1 to clear.
0
Signaled System Error: This bit is set whenever the CS4210 asserts
SERR# active.
Write 1 to clear.
0
Received Master Abort: This bit is set whenever a master abort cycle
occurs while the CS4210 is the master for the PCI cycle.
Write 1 to clear.
0
Received Target Abort: This bit is set whenever a target abort is received
while the CS4210 is the master for the PCI cycle.
Write 1 to clear.
0
Signaled Target Abort: This bit is set whenever the CS4210 signals a tar-
get abort while it is the target for the PCI cycle.
Write 1 to clear.
01
DEVSEL# Timing: These bits are always 01, as the CS4210 always
responds to cycles for which it is an active target with medium DEVSEL#
timing: 00 = Fast; 01 = Medium; 10 = Slow; 11 = Reserved
0
Data Parity Detected: This bit is set when the CS4210 asserted PERR# or
observed PERR# asserted. The parityErrResp in the Command Register
(Index 04h[6]) must be enabled for this bit to function.
Write 1 to clear.
0
Reserved
Index 08h
Revision Identification Register
7:0
revisionID
RO
03h Revision Identification: Specifies the silicon revision as 03h. This value
will be incremented for subsequent revisions.
Index 09h
23:16
15:8
7:0
Index 0Ch
Base Class
Sub Class
Programming
Interface
PCI Class Code Register
RO
0Ch Base Class: Identifies the device as being a serial bus controller.
RO
00h Sub Class: Identifies the device as being of IEEE 1394 class.
RO
10h Programming Interface: Identifies the device as being a 1394 OpenHCI
controller.
PCI Cache Line Size Register
7:0
cacheLineSize
RO
00h PCI Cache Line Size: This register sets the size of the PCI cache line. A
value of 00h indicates caching is disabled.
Index 0Dh
PCI Latency Timer Register
7:0
latencyTimer
R/W
50h PCI Latency Timer Value: This register contains the maximum number of
PCI clocks that the CS4210 can hold ownership of the PCI bus as the bus
master. Bits [3:0] are a constant 0.
Index 0Eh
PCI Header Type Register
7:0
Header Type
Index 0Fh
RO
00h PCI Header Type Register: This register defines the format of this header.
This header is of type format 0. Additionally, bit 7 defines whether this PCI
device is a multi-function (bit 7 = 1) or single-function (bit 7 = 0) device.
PCI BIST Register
7:0
BIST
RO
00h PCI Built-In Self-Test: A value of 00h indicates no PCI controlled BIST.
Revision 1.0
43
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