CS4210 Datasheet, PDF (91/102 Pages) National Semiconductor (TI) – IEEE 1394 OHCI Controller

Register Descriptions (Continued)
4.5.1 nscControl Register
The nscControl register (Table 4-57) is used to control fea-
tures of the CS4210 that are not defined within the Open-
HCI standard registers. This register may be configured via
the serial EEPROM interface.
Bit
31:22
21
20
19
18
17:16
14
13
12
11
10
9
8
7
6
5
4
Table 4-57. BAR1+Offset 00h: nscControl Register
Name
Access Reset Description
RSVD
---
busHoldEnab
RW
PCICapabilities
RW
testOutSel
RW
fastEpromMode
RW
altMode
RW
programPhyEnab
RW
aPhyEnhanEnab
RW
linkSpdWp
RW
disableCmDetect
RW
noCycleMaster
RWU
altAckConcat
RW
RSVD
--
altAckAccel
RW
altMultiSpd
RW
altIdleInsert
RW
RSVD
--
0
Reserved
0
Bus Hold Enable: Allow bus holders for single capacitor isolation.
0 = Disable; 1 = Enable.
0
PCI Capabilities: Allow the PCI power management structures to be visible
in the PCI configuration header. 0 = Disable; 1 = Enable.
See Table 4-6: "Index 44h Capability ID Register" on page 45, "Index 46h-
47h Power Management Capabilities Register" on page 46, and "Index 48h
Power Management and Control Status Register" on page 46.
0
Test Out Pin Select: Selects function of TESTO pin (pin 7).
0 = TESTO is the output of the NAND tree.
1 = TESTO pin reflects RAM BIST status.
0
Fast EEPROM Mode: Allow fast operation of the EEPROM interface for
test purposes. 0 = Disable; 1 = Enable.
00
Alternate Mode: Modifier for aPhyEnhanceEnable and the alt bits in this
register. See Table 4-58 "altMode" on page 92 for details.
0
Program PHY Enable: Mirror of HCControl.programPhyEnable bit
(BAR0+Offset 50h[23]).
0
A PHY Enhancement Enable: Mirror of HCControl.aPhyEnhanceEnable
bit (BAR0+Offset 50h[22]).
0
Link Speed Write Protect: Makes BusOptions.link_spd field (BAR0+Offset
20h[2:0]) read only. 0 = Disable; 1 = Enable.
0
Disable Cycle Master Detector: Turn-off the no cycle master detector
logic. 0 = Disable; 1 = Enable.
When this bit is set, the link layer logic that detects the absence of a cycle
master is disabled. This detector is not a standard feature of the OpenHCI
specification, thus this bit is defined to handle any unforeseen interoperabil-
ity issues. If the noCycleMaster bit is also set, then setting this bit will have
no effect.
0
No Cycle Master: Force an internal “no cycle master present” condition.
0 = Disable; 1 = Enable.
Setting this bit overrides the cycle master detector logic. When this bit is
clear, the link layer must observe 255 consecutive cycle lost events before
concluding that no cycle master node is present.
0
Alternate Acknowledge Concatenation: Modify the interpretation of the
HCControl.aPhyEnhanceEnable bit (BAR0+Offset 50h[23]) with respect to
concatenation of packets onto the transmission of handshake packets. See
altMode (bits [17:16]) and Table 4-58 "altMode" on page 92 for details.
0
Reserved
0
Alternate Acknowledge Accelerate: Modify the interpretation of the
HCControl.aPhyEnhanceEnable bit (BAR0+Offset 50h[23]) with respect to
ACK accelerated arbitration. When enabled the link layer will not consider
the media “lost” when receiving a handshake packet. See altMode (bits
[17:16]) and Table 4-58 "altMode" on page 92 for details.
0
Alternate Multispeed: Modify the interpretation of the HCControl.aPhyEn-
hanceEnable bit (BAR0+Offset 50h[23]) with respect to multispeed packet
concatenation. See altMode (bits [17:16]) and Table 4-58 "altMode" on
page 92 for details.
0
Alternate Idle Insert: Modify the interpretation of the HCControl.aPhyEn-
hanceEnable bit (BAR0+Offset 50h[23]) with respect to the signaling per-
formed by the link when it has been granted permission to transmit. See
altMode (bits [17:16]) and Table 4-58 "altMode" on page 92 for details.
0
Reserved
Revision 1.0
91
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