CS4210 Datasheet, PDF (68/102 Pages) National Semiconductor (TI) – IEEE 1394 OHCI Controller

Register Descriptions (Continued)
4.4.13 Self-ID Buffer Pointer Register
The Self-ID Buffer Pointer register (Table 4-23) points to
the buffer the Self-ID packets are DMA’ed into during bus
initialization.
4.4.14 Self-ID Count Register
The Self-ID Count register (Table 4-24) keeps a count of
the number of times the bus Self-ID process has occurred,
flags Self-ID packet errors and keeps a count of the
amount of Self-ID data in the Self-ID buffer.
Bit
31:11
10:0
Table 4-23. BAR0+Offset 64h: Self-ID Buffer Pointer Register
Name
selfIDBufferPtr
RSVD
Access
RW
--
Reset
Undef
0
Description
Self-ID Buffer Pointer: Contains the 2 KB aligned base address of the
buffer in host memory where received Self-ID packets are stored. The con-
tents of this field are undefined after a chip reset.
Reserved
Bit
31
30:24
23:16
15:13
12:2
1:0
Table 4-24. BAR0+Offset 68h: Self-ID Count Register
Name
Access Reset Description
selfIDError
RU
Undef Self-ID Error: When this bit is one, an error was detected during the most
recent Self-ID packet reception. The contents of the Self-ID buffer are unde-
fined. This bit is cleared after a Self-ID reception in which no errors are
detected. Note that an error can be a hardware error or a host bus write
error.
RSVD
--
0
Reserved
selfIDGeneration
RU
Undef Self-ID Generation: The value in this field increments each time a bus
reset is detected. This field rolls over to 0 after reaching 255.
RSVD
--
0
Reserved
2selfIDSize
RU
Undef Quadlet Self-ID Size: This field indicates the number of quadlets that have
been written into the Self-ID buffer for the current Self-ID Generation. This
includes the header quadlet and the Self-ID data. This field is cleared to
zero as soon as a bus reset is detected.
RSVD
--
0
Reserved
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