CS4210 Datasheet, PDF (62/102 Pages) National Semiconductor (TI) – IEEE 1394 OHCI Controller

Register Descriptions (Continued)
4.4.7 Bus Options Register
The Bus Options register (Table 4-16) is a 32-bit number
that externally maps to the second quadlet of the
Bus_Info_Block. This register is written locally at
BAR0+Offset 20h. This register is loaded from the serial
EEPROM, if present, which sets the values after a hard-
ware reset.
Bit
31:27
30
29
28
27
26:24
23:16
15:12
11:8
7:6
5:3
2:0
Name
irmc
cmc
isc
bmc
pmc
RSVD
cyc_clk_acc
max_rec
RSVD
g
RSVD
link_spd
Table 4-16. BAR0+Offset 20h: Bus Options Register
Access
RW
RW
RW
RW
RW
--
RW
RW
--
RW
--
RWU
RU
Reset
Undef
Undef
Undef
Undef
Undef
0
Undef
**
0
Undef
0
**
Description
Isochronous Resource Manager Capable: IEEE 1394 bus management
field. Must be valid at any time the HCControl.linkEnable bit (BAR0+Offset
50h[17]) is set.
Cycle Manager Capable: IEEE 1394 bus management bit. Must be valid at
any time the HCControl.linkEnable bit (BAR0+Offset 50h[17]) is set.
Isochronous Capable: IEEE 1394 bus management bit. Must be valid at
any time the HCControl.linkEnable bit (BAR0+Offset 50h[17]) is set.
Bus Manager Capable: IEEE 1394 bus management bit. Must be valid at
any time the HCControl.linkEnable bit (BAR0+Offset 50h[17]) is set.
Power Manager Capable: IEEE 1394 bus management bit. Must be valid
at any time the HCControl.linkEnable bit (BAR0+Offset 50h[17]) is set.
Reserved
Cycle Clock Access: IEEE 1394 bus management field. Must be valid at
any time the HCControl.linkEnable bit (BAR0+Offset 50h[17]) is set.
Maximum Received: IEEE 1394 bus management field. Hardware initial-
izes max_rec to 1024 if no serial EEPROM is used or to the value stored for
this register in the EEPROM if present. Software may change max_rec,
however, this field must be valid at any time the HCControl.linkEnable bit
(BAR0+Offset 50h[17]) is set to 1. Note that received block write request
packets with a length greater than max_rec shall generate an
ack_type_error if the request is not handled by the physical response unit,
and may generate an ack_type_error otherwise.
** Reset values: For a hardware reset, max_rec is set 1024 or to the value
stored in the serial EEPROM, if present. For a soft reset, max_rec is not
changed.
Reserved
Generation Counter: This field increments if any portion of configuration
ROM has changed since the prior bus reset.
Reserved
Link Speed: 000 = 100 Mbits/sec; 001 = 200 Mbits/sec; 010 = 400 Mbits/
sec; all other values are reserved.
**On a hardware reset, link_spd is set 010 (400 Mbits/sec) or to the value
stored in the serial EEPROM, if present. If the link_spd write protect in the
nscControl register (BAR1+Offset 00h[12]) is not set, software is permitted
to change link_spd to a lower value, which causes the link to reject packets
arriving at higher speeds.
**On a software reset, the value of link_spd is undefined.
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