CS4210 Datasheet, PDF (29/102 Pages) National Semiconductor (TI) – IEEE 1394 OHCI Controller

Operational Description (Continued)
3.7.3 Isochronous Transmit Data Write Error
A data write error can occur when the CS4210 attempts to
write to the address indicated in a STORE_VALUE descrip-
tor. This error is handled like a data read error with the
exception that the event code is set to evt_data_write. The
CS4210 does not begin placing the packet associated with
a STORE_VALUE into the output FIFO until the
STORE_VALUE operation is complete. This is to prevent
the possibility of having multiple errors that cannot be prop-
erly reported to system software.
3.7.4 Asynchronous Receive DMA Data Write Error
When a host bus error occurs while the CS4210 is attempt-
ing to write to either the request or response buffer, the
CS4210 sets the corresponding ContextControl.dead and
set ContextControl.event to evt_data_write. The unrecover-
able error IntEvent is generated and the context’s IntEvent
is not set regardless of the setting of the interrupt (i) field in
the descriptor. CommandPtr.descriptorAddress points to
the descriptor that contained the buffer descriptor for the
memory address at which the error occurred. Any data in
the input FIFO for the context is discarded.
3.7.5 Isochronous Receive Data Write Error
If a data write error occurs for a context that is in packet-
per-buffer mode, the CS4210 sets ContextControl.event to
evt_data_write or evt_overrun and conditionally updates
xferStatus of the descriptor in which the error occurred.
Any remaining data in the input FIFO for the packet is dis-
carded. The resCount value in a descriptor that has an
error will not necessarily reflect the correct number of data
bytes successfully written to memory. If a FIFO overrun
occurs for a context that is in buffer-fill mode, the packet is
treated as if a data length error had occurred and is
‘backed out’ of the receive buffer (xferStatus and resCount
not updated) and the remainder of the packet is discarded
from the input FIFO. If a host bus error occurs for a context
in buffer-fill mode, the CS4210 sets ContextControl.dead
and sets ContextControl.event to evt_data_write. The unre-
coverable error IntEvent is generated and the context’s
IntEvent is not set regardless of the setting of the interrupt
(i) field in the descriptor. CommandPtr.descriptorAddress
points to the descriptor that contained the buffer descriptor
for the memory address at which the error occurred. Any
data in the input FIFO for the context is discarded.
3.7.6 Physical Read Error
When an external node does a physical access and the
CS4210’s read of system memory fails, the CS4210
returns an error indication to the requester by forming a
response containing a response code of resp_data_error. If
the device replies with ack_busy or ack_data_error the host
retries the packet. If the error was caused by a FIFO under-
run, the CS4210 retries with the same response. If the
error was a host bus error, the response packet is changed
to resp_data_error.
3.7.7 Posted Write Error
Whether to be handled by the Physical Request controller
or by the Asynchronous Receive Request context, write
requests to certain address ranges (see Section 3.6 "Phys-
ical Requests" on page 26) may be acked with
ack_complete before the data is actually written to system
memory. Since the sending node has been notified that the
action is complete, when the CS4210 cannot complete a
posted write operation due to a host bus error the system
must be notified so that software can recover.
If an error occurs in writing the posted data packet, then the
CS4210 sets the IntEvent.PostedWriteErr bit (BAR0+Offset
80h[8]) to indicate that an error has occurred and the write
remains pending. Software can then read the source node
ID and offset address from the PostedWriteAddress regis-
ter and then clear IntEvent.PostedWriteErr. When software
clears IntEvent.PostedWriteErr, that write is no longer
pending.
Although the CS4210 allows four pending writes, error
reporting is through a single pair of software visible regis-
ters. If multiple posted write failures have occurred, soft-
ware accesses them one at a time through the
PostedWriteAddress register. When software clears
IntEvent.PostedWriteErr, this is a signal to the CS4210 that
software has completed reading of the current contents of
PostedWriteAddress and that the CS4210 can report
another error by again setting IntEvent.PostedWriteErr and
presenting a new set of values when software reads Post-
edWriteAddress. Table 3-10 provides a map of the Posted-
WriteAddress register. Refer to Section 4.4.10
"PostedWriteAddress Register" on page 64 for further reg-
ister information.
If the CS4210 has four pending physical writes, additional
physical writes may not be posted. Instead the CS4210
returns ack_pending and only returns a complete indication
when the write is actually done.
Table 3-10. BAR0+Offset 38h: PostedWriteAddress Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
sourceID
offsetLo
offsetHi
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