CS4210 Datasheet, PDF (6/102 Pages) National Semiconductor (TI) – IEEE 1394 OHCI Controller

1.0 Architectural Description
The CS4210 device implements an IEEE 1394 serial bus
host controller as specified by the OHCI Specification Ver-
sion 1.0. It is organized as a collection of reusable modules
as illustrated in Figure 1-1.
The interface to the 1394 bus is organized into three clock
domains: PCI, SCLK, and SCLK/2. The PCI clock domain
can operate at up to 33 MHz. The PCI clock can also be
stopped. The SCLK clock domain operates at 49.152 MHz.
The SCLK/2 clock domain operates at 24.576 MHz.
1.1 PCI INTERFACE MODULE
The PCI interface module provides a full function bus mas-
tering interface to the PCI bus.
1.2 DMA ENGINE
The DMA engine is decomposed into four functional mod-
ules:
• TE: Transfer Engine
— Provides generic data movement services to the rest
of the DMA engine logic.
• ATDMA: Asynchronous Transmit DMA
— Controls the transmission of all asynchronous
packets.
• ITDMA: Isochronous Transmit DMA
— Controls the transmission of all isochronous packets.
• RDMA: Receive DMA
— Processes all received packets (asynchronous,
isochronous and physical) and transmit status.
A single port SRAM is shared by the DMA logic for caching
control information and descriptor blocks fetched from the
host memory. This RAM is used for capturing entire
descriptor blocks in a single PCI bus tenure.
PCI Interface
FM_Bus (Slave)
FM_Bus (Master)
Arbiter
I²C Bus
Register
DMA Engine
RDMA
Set
ITDMA
ATDMA
AR
IR Phys
TE
Clock Generator
and Power
Management
SCLK LNKON LPS
Tx FIFO
(SRAM)
Tx FIFO
(SRAM)
Scratchpad
(SRAM)
Rx FIFO
(SRAM)
Tx Drain
Link Layer
Physical Layer Interface (49.152 MHz)
Rx Fill
LREQ
DATA[0:7]
CTRL[0:1]
Figure 1-1. Functional Block Diagram
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Revision 1.0