CS4210 Datasheet, PDF(87/102 Page) National Semiconductor (TI)

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CS4210 Datasheet, PDF (87/102 Pages) National Semiconductor (TI) – IEEE 1394 OHCI Controller

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Bit

27:16

14:13

9:8

7:5

4:0

Table 4-53. IsochRxnContextControl Set/Clear Register

Name

bufferFill

Access

RSC

isochHeader

RSC

cycleMatchEnable RSCU

multiChanMode

RSC

RSVD

run

RSCU

RSVD

wake

dead

active

RSVD

spd

event code

RSU

Reset

Undef

Description

Buffer Fill: When set to one, received packets are placed back-to-back to

completely fill each receive buffer (specified by an INPUT_MORE com-

mand). When clear, each received packet is placed in a single buffer

(described by zero to seven INPUT_MORE commands followed by an

INPUT_LAST command). If the multiChanMode bit (bit 28) is set to one,

this bit must also be set to one. The value of bufferFill must not be changed

while active (bit 10) or run (bit 15) are set to one.

Isochronous Header: When set to one, received isochronous packets

include the complete 4-byte isochronous packet header seen by the Link

layer. The end of the packet is marked with a xferStatus (bits 15:0 of this

the most recently received (or sent) cycleStart packet. When clear, the

packet header is stripped off of received isochronous packets. The packet

header, if received, immediately precedes the packet payload. Details are in

the 1394 OHCI specification data formats. The value of isochHeader must

not be changed while active or run are set to one.

Cycle Match Enable: In general, when set to one, the context begins run-

ning only when the 15-bit cycleMatch field in the corresponding IsochRxn-

ContextMatch register matches the two sets of bits of the bus

IsochCycleTimer.cycleSeconds and 13-bit IsochCycleTimer.cycleCount val-

ues (BAR0+Offset F0h). The effects of this bit are impacted by the values of

other bits in this register and are explained in Section 4.4.26.1 "Isoch Trans-

mit Context Control Register" on page 84. Once the context has become

active, hardware clears the cycleMatchEnable bit. The value of cycleMatch-

Enable must not be changed while active or run are set to one.

Multiple Channel Mode: When set to one, the corresponding isochronous

receive DMA context receives packets for all isochronous channels enabled

in the IRChannelMaskHi and IRChannelMaskLo registers (Section 4.4.15

"IRMultiChanMask Registers" on page 69). The isochronous channel num-

ber specified in the corresponding IsochRxnContextMatch register is

ignored. When set to zero, the IRDMA context receives packets for that sin-

gle channel. Only one IRDMA context may use the IRChannelMask regis-

ters. If more than one IsochRxContextControl register has the

multiChanMode bit set, results are undefined. The value of multiChanMode

must not be changed while active or run are set to one

Reserved

Run: The run bit is set by software to enable descriptor processing for a

context and cleared by software to stop descriptor processing. The CS4210

only clears this bit on a hardware or software reset. See Section 3.3.2.1

"ContextControl.run" on page 21 for details.

Reserved

Wake: Software sets this bit to 1 to cause the CS4210 to continue or

resume descriptor processing. The CS4210 clears this bit on every descrip-

tor fetch. See Section 3.3.2.2 "ContextControl.wake" on page 21 for details.

Dead: The CS4210 sets this bit when it encounters a fatal error and clears

this bit when software clears the run bit. See Section 3.3.2.4 "ContextCon-

trol.dead" on page 21 for details.

Active: The CS4210 sets this bit to 1 when it is processing descriptors. See

Section 3.3.2.3 "ContextControl.active" on page 21 for details.

Reserved

Speed: This field indicates the speed at which the packet was received.

000 = 100 Mbits/sec, 001 = 200 Mbits/sec, and 010 = 400 Mbits/sec. All

other values are reserved.

Event Code: For bufferFill mode, possible values are: ack_complete,

evt_descriptor_read, evt_data_write, and evt_unknown. Packets with data

errors and packets for which a FIFO overrun occurred are âbacked-outâ by

reverting to the previous state and Xferstatus and resCount are not

updated. For packet-per-buffer mode, possible values are: ack_complete,

ack_data_error, evt_long_packet, evt_overrun, evt_descriptor_read,

evt_data_write, and evt_unknown.

Revision 1.0

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