CS4210 Datasheet, PDF (66/102 Pages) National Semiconductor (TI) – IEEE 1394 OHCI Controller

Register Descriptions (Continued)
Table 4-21. BAR0+Offset 50h (Set) and 54h (Clear): HCControl Register (Continued)
Bit
18
17
16
15:0
Name
postedWriteEnable
Access
RSC
linkEnable
RSU
softReset
RSU
RSVD
--
Reset
Undef
0
**
0
Description
Posted Write Enable: This bit is used to enable (1) or disable (0) physical
posted writes. When disabled (0), physical writes are handled but are
posted and instead are ack’ed with ack_pending.
Software should change this bit only when linkEnable (bit 17) is 0, other-
wise unspecified behavior results. See Section 3.6 "Physical Requests" on
page 26 for information about posted writes.
Link Enable: Software must set this bit to 1 when the system is ready to
begin operation and then force a bus reset. This bit is necessary to keep
other nodes from sending transactions before the local system is ready.
When this bit is clear the CS4210 is logically and immediately disconnected
from the 1394 bus. The link will not process or interpret any packets
received from the CS4103, nor will it generate any bus requests. However,
the link will access CS4103 registers via the CS4103 control register.
This bit is cleared to 0 by a hardware reset or software reset, and must not
be cleared by software. Software must not set the linkEnable bit until the
Configuration ROM mapping register (Section 4.4.9 on page 63) is valid.
Soft Reset: When set to 1, the CS4210’s state is reset, all FIFO’s are
flushed and all CS4210 OHCI registers are set to their hardware reset val-
ues unless otherwise specified. Registers outside of the OpenHCI realm
(i.e., PCI and NSC defined registers) are not affected.
**The read value of this bit is 1 while a soft reset or a hard reset is in
progress. The read value of this bit is 0 when neither a soft reset nor hard
reset are in progress. Software can use the value of this bit to determine
when a reset has completed and the CS4210 is safe to operate.
Reserved
4.4.12.1 noByteSwapData
The 1394 bus is quadlet based big endian. By convention,
when quadlets are sent in big endian order, the leftmost
byte (bits [31:24]) of a quadlet is sent first. When sent in lit-
tle endian order, the right most byte (bits [7:0]) is sent first
with the leftmost bit of each byte sent first.
When the CS4210 sends/receives a packet, the header
information is always sent/received in big endian order
(leftmost byte first). Header information is composed of a
sequence of quadlets which is invariant over big and little
endian system.
When the HCControl.noByteSwapData bit is not set, data
quadlets are sent/received in little endian order and when
HCControl.noByteSwapData is set, data quadlets are sent/
received in big endian order. The data quadlets as classi-
fied by the OHCI transaction codes (tcodes) that are sub-
ject to swap are:
1) Any data quadlet covered by data CRC (tcodes 1h, 7h,
9h, Ah, and Bh).
2) The data quadlet in a quadlet write request (tcode 0h).
3) The data quadlet in a quadlet read response (tcode
6h).
Since the cycle_time is self contained within the CS4210, it
is never byte-swapped regardless of the setting of the
noByteSwapData bit.
The data in a PHY packet (identified internally with tcode
Eh) is not byte swapped for send or receive.
Note: Due to some confusion regarding this bit, an expla-
nation and some examples are available on the
OpenHCI FTP site.
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