CS4210 Datasheet, PDF (65/102 Pages) National Semiconductor (TI) – IEEE 1394 OHCI Controller

Register Descriptions (Continued)
4.4.12 HCControl Register
The HCControl register (Table 4-21) provides flags for con-
trolling the CS4210. There are two addresses for this regis-
ter:
1) BAR0+Offset 50h: HCControl Set
2) BAR0+Offset 54h: HCControl Clear
On read, both addresses return the contents of the control
register. For writes, the two addresses have different
behavior: a one bit written to HCControl Set causes the
corresponding bit in the HCControl register to be set, while
a zero bit leaves the corresponding bit in the HCControl
register unaffected. On the other hand, a one bit written to
HCControl Clear causes the corresponding bit in the
HCControl Set register to be cleared, while a zero bit
leaves the corresponding bit in the HCControl Set register
unaffected.
Bit
31
30
29:24
23
22
21:20
19
Table 4-21. BAR0+Offset 50h (Set) and 54h (Clear): HCControl Register
Name
Access Reset Description
RSVD
noByteSwapData
--
RSC
RSVD
--
programPhyEnable
RC
aPhyEnhanceEnable RSC
RSVD
--
LPS
RS
0
Undef
0
1
0
0
0
Reserved
No Byte Swap Data: This bit is used to control whether physical accesses
to locations outside the CS4210 itself as well as any other DMA data
accesses should be swapped or not. When 0, data quadlets are sent/
received in little endian order. When 1, data quadlets are sent/received in
big endian order. See Section 4.4.12.1 "noByteSwapData" on page 66 for
further information. Software should change this bit only when linkEnable
(bit 17) is 0, otherwise unspecified behavior results.
Reserved
Program PHY Enable: This bit informs upper-level generic software (e.g.,
OHCI device driver) if lower-level implementation specific software (e.g.,
BIOS or Open Firmware) has consistently configured P1394a enhance-
ments in the CS4210 and CS4103. If the implementation does not support
P1394a enhancements, lower-level implementation specific software must
clear this bit.
When 1 and while linkEnable (bit 17) is 0, generic software is responsible
for configuring the P1394a enhancements within the CS4103 and the aPhy-
EnhanceEnable bit within the CS4210 Link in a consistent manner.
When 0, generic software may not modify the P1394a enhancement config-
uration in either the CS4210 or CS4103 and cannot interpret the setting of
aPhyEnhanceEnable.
A soft reset and a bus reset do not affect this bit.
A PHY Enhancement Enable: When the programPhyEnable bit is 1, this
bit is used by generic, implementation independent software (e.g., OHCI
device driver) to enable the CS4210 Link to use all of P1394a enhance-
ments. Generic software can only modify this bit when the programPhyEn-
able bit is 1 and the linkEnable (bit 17) bit is 0. This bit is meaningless to
software when the programPhyEnable bit is 0.
When 0, none of the P1394a enhancements are enabled within the Link.
When 1, the set of all P1394a enhancements is enabled within the Link.
A soft reset and a bus reset do not affect this bit.
See Section 4.4.12.2 "programPhyEnable and aPhyEnhanceEnable" on
page 67 for more information.
Reserved
Link Power Status: Software must set LPS to 1 to permit CS4210/CS4103
communication. Once set, the link can use LREQs to perform CS4103
reads and writes.
An LPS value of 0 prevents CS4210/CS4103 communication. In this state,
the only accessible CS4210 registers are Version, VendorID, HCControl,
GUID_ROM, GUIDHi and GUIDLo. Access to other registers is not defined.
Hardware and software resets clear LPS to 0. Software shall not clear LPS.
See the Section 4.4.12.3 "LPS and linkEnable" on page 67 for more infor-
mation.
Revision 1.0
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