CS4210 Datasheet, PDF (13/102 Pages) National Semiconductor (TI) – IEEE 1394 OHCI Controller

Signal Definitions (Continued)
2.2.1 PCI Bus Interface Signals (Continued)
Signal Name
Pin No.
Type Description
RST#
PCLK
PME#
10
I
PCI Reset
RST# is driven low to reset the device.
12
I
Clock
0-33 MHz PCI clock.
17
O
Power Management Event
PCI power management pin as defined in the PCI Bus Power Management
Specification Revision 1.1.
2.2.2 PHY-Link Interface Signals
Signal Name
Pin No.
I/O
DATA[0:7]
81, 82, 84,
I/O
85, 86, 88,
89, 90
CTRL[0:1]
93, 92
I/O
LREQ
SCLK
97
O
95
I
LPS
LNKON
DIRECT
99
O
98
I
79
I
Description
PHY Data
Bidirectional data lines driven by both the Link and PHY layer modules. The
width of the data bus depends on the speed of data transfer rate. Packet rate
for 100 Mbit/sec transfers use DATA[0:1], 200 Mbit/sec transfers use
DATA[0:3], 400 Mbit/sec transfers use DATA[0:7].
Note: DATA0 is considered the MSB (most significant bit) based upon the
IEEE 1394-1995 specification.
Control bits 1 and 0
Bidirectional handshaking signals driven by both the Link and PHY layer
modules. The CS4210 and CS4103 use these signals to arbitrate the control
of the PHY-Link interface. The control bits also indicate the type of transfer
communicating between the two layers namely idle, status, receive, and
transmit.
Link Request
Used by the CS4210 to request access of the 1394 bus and to read/write the
internal registers of the CS4103.
Sync Clock
The 49.152 MHz clock input driven by the CS4103’s PLL block synchronized
to the 1394 bus clock. This clock is also used to synchronize the LREQ,
CTRL[0:1], and DATA[0:7] communication protocol between the CS4210
and CS4103.
Link Power Status
Indicates the power status of the CS4210. If LPS is low indicating the
CS4210 is not powered, the signals CTRL[0:1], DATA[0:7], and SCLK con-
nected to the CS4210 are disabled.
Link On
Indicates to the CS4210 that the CS4103 has received a Link-On packet
addressed to this node.
Direct
High indicates direct connection. Low indicates isolation barrier. Set high
when using the single capacitor bus hold isolation.
Revision 1.0
13
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