CS4210 Datasheet, PDF (84/102 Pages) National Semiconductor (TI) – IEEE 1394 OHCI Controller

Register Descriptions (Continued)
4.4.26 Isochronous Transmit
Each isochronous transmit context consists of two regis-
ters: CommandPtr and ContextControl. CommandPtr is
used by software to tell the ITDMA controller where the
DMA context program begins. IsochTxContextControl is
used by software to control the context’s behavior, and is
used by hardware to indicate current status.
The CS4210 has eight isochronous transmit contexts.
These registers are repeated at offsets of 10h times the
context number. Table 4-49 is a map providing the offset
addresses for the isochronous transmit ContextControl and
CommandPtr registers.
Table 4-49. IsochTx Register Address Map
BAR0+Offset Name
200h
204h
208h
20Ch
210h
214h
218h
21Ch
220h
224h
228h
22Ch
230h
234h
238h
23Ch
240h
244h
248h
24Ch
250h
254h
258h
25Ch
260h
264h
268h
26Ch
270h
274h
278h
27Ch
IsochTx0ContextControl Set Register
IsochTx0ContextControl Clear Register
Reserved
IsochTx0CommandPtr Register
IsochTx1ContextControl Set Register
IsochTx1ContextControl Clear Register
Reserved
IsochTx1CommandPtr Register
IsochTx2ContextControl Set Register
IsochTx2ContextControl Clear Register
Reserved
IsochTx2CommandPtr Register
IsochTx3ContextControl Set Register
IsochTx3ContextControl Clear Register
Reserved
IsochTx3CommandPtr Register
IsochTx4ContextControl Set Register
IsochTx4ContextControl Clear Register
Reserved
IsochTx4CommandPtr Register
IsochTx5ContextControl Set Register
IsochTx5ContextControl Clear Register
Reserved
IsochTx5CommandPtr Register
IsochTx6ContextControl Set Register
IsochTx6ContextControl Clear Register
Reserved
IsochTx6CommandPtr Register
IsochTx7ContextControl Set Register
IsochTx7ContextControl Clear Register
Reserved
IsochTx7CommandPtr Register
4.4.26.1 Isoch Transmit Context Control Register
The IsochTxContextControl Set/Clear registers (Table 4-50
on page 85) contain bits that control options, operational
state, and status for the ITDMA contexts. Software can set
selected bits by writing ones to the corresponding bits in
the ContextControl Set register. Software can clear
selected bits by writing ones to the corresponding bits in
the ContextControl Clear register. It is not possible for soft-
ware to set some bits and clear others in an atomic opera-
tion. A read from either register returns the same value.
In addition to the standard ContextControl fields, it includes
a mechanism for starting transmit at a specified cycle time.
The cycleMatch field is used to start an ITDMA context pro-
gram on a specified cycle. Software enables matching by
setting the cycleMatchEnable bit. When the low order two
bits of the bus IsochCycleTimer.cycleSeconds and Isoch-
CycleTimer.cycleCount (BAR0+Offset F0h) value matches
the cycleMatch value, hardware clears the cycleMatchEn-
able bit to 0, sets the ContextControl.active bit to 1, and
begins executing descriptor blocks for the context. The
transition of an ITDMA context to the active state from the
not-active state is dependent upon the values of the run
and cycleMatchEnable bits.
If run transitions to 1 when cycleMatchEnable is 0, then the
context becomes active (active = 1).
If both run and cycleMatchEnable are set to 1, then the
context becomes active when the low order two bits of the
bus IsochCycleTimer.cycleSeconds and 13-bit IsochCy-
cleTimer. cycleCount values match the 15-bit cycleMatch
value.
If both run and cycleMatchEnable are set to 1, and cycleM-
atchEnable is subsequently cleared, the context becomes
active.
If both run and active are 1 (the context is active), and then
cycleMatchEnable is set to 1, this results in unspecified
behavior.
Due to software latencies, software attempts to manage
the startup of a context too close to the current time may
not be effective.
In addition, the usability of cycleMatchEnable for IT con-
texts is impacted by the cycleInconsistent interrupt. Refer
to Section 3.2.3.3 "Isoch Tx and Rx Context Interrupts" on
page 17 for more information.
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