CS4210 Datasheet, PDF (77/102 Pages) National Semiconductor (TI) – IEEE 1394 OHCI Controller

Register Descriptions (Continued)
4.4.20 PHYControl Register
The PHYControl register (Table 4-35) is used to read or
write a CS4103 register. To read a register, the address of
the register is written to the regAddr field along with a 1 in
the rdReg bit. When the read request has been sent to the
CS4103 (through the LREQ pin), the rdReg bit is cleared to
0. When the CS4103 returns the register, the rdDone bit
transitions to 1 and the IntEvent.phyRegRcvd interrupt
(BAR0+Offset 80h[26]) is set. The address of the register
received is placed in the rdAddr field and the contents in
the rdData field. Software must not issue a read of CS4103
register 0. The most recently available contents of this reg-
ister is reflected in the NodeID register (see Section 4.4.19
"Node ID and Status Register" on page 76). To write to a
CS4103 register, the address of the register is written to
the regAddr field, the value to write to the wrData field, and
a 1 to the wrReg bit. The wrReg bit is cleared when the
write request has been transferred to the CS4103. Soft-
ware must serialize all CS4103 register reads and writes.
Only after the current CS4103 register read or write com-
pletes may software issue a different CS4103 register read
or write.
4.4.21 IsochCycleTimer Register
The IsochCycleTimer register (Table 4-36) is a read/write
register that shows the current cycle number and offset.
The cycle timer register is split up into three fields. The
lower order 12 bits are the cycle offset, the middle 13 bits
are the cycle count, and the upper order 7 bits count time in
seconds. When the CS4210 is cycle master, this register is
transmitted with the cycle start message. When the
CS4210 is not the cycle master, this register is loaded with
the data field in each incoming cycle start. In the event that
the cycle start message is not received, the fields continue
incrementing on their own (when cycleTimerEnable is set
in the LinkControl register, BAR0+Offset E0h[20]) to main-
tain a local time reference.
Bit
31
30:28
27:24
23:16
15
14
13:12
11:8
7:0
Name
rdDone
RSVD
rdAddr
rdData
rdReg
wrReg
RSVD
regAddr
wrData
Table 4-35. BAR0+Offset ECh: PHYControl Register
Access
RU
--
RU
RU
RWU
RWU
--
RW
RWU
Reset
Undef
0
Undef
Undef
0
0
0
Undef
Undef
Description
Read Done: rdDone is cleared to 0 by the CS4210 when either rdReg or
wrReg is set to 1. This bit is set to 1 when a register transfer is received
from the CS4103.
Reserved
Read Address: This is the address of the register most recently received
from the CS4103.
Read Data: Contains the data read from the CS4103 register at rdAddr.
Read Register: Set rdReg to initiate a read request to a CS4103 register.
This bit is cleared when the read request has been sent. The wrReg bit
must not be set while the rdReg bit is set.
Write Register: Set wrReg to initiate a write request to a CS4103 register.
This bit is cleared when the write request has been sent. The rdReg bit
must not be set while the wrReg bit is set.
Reserved
Register Address: regAddr is the address of the CS4103 register to be
written or read.
Write Data: This is the contents to be written to a CS4103 register. Ignored
for a read.
Bit
31:25
24:12
11:0
Table 4-36. BAR0+Offset F0h: IsochCycleTimer Register
Name
cycleSeconds
cycleCount
cycleOffset
Access
RWU
RWU
RWU
Reset
N/A
N/A
N/A
Description
Cycle Seconds: This field counts seconds (cycleCount rollovers) modulo
128.
Cycle Count: This field counts cycles (cycleOffset rollovers) modulo 8000.
Cycle Offset: This field counts 24.576 MHz clocks modulo 3072, (i.e., 125
µs). If an external 8 kHz clock configuration is being used, cycleOffset is set
to 0 at each tick of the external clock.
Revision 1.0
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