CS4210 Datasheet, PDF (44/102 Pages) National Semiconductor (TI) – IEEE 1394 OHCI Controller

Register Descriptions (Continued)
Table 4-6. PCI Configuration Register Definitions
Bit
Name
Access Reset Description
Index 10h
Base Address Register 0 (BAR0)
This register specifies the base address of a contiguous memory space in the PCI memory space of the host. This memory space is
assigned to the configuration and operational registers defined by the OHCI specification. The registers designated as the CS4210 Con-
figuration Registers (listed in Section 4.4 "OHCI Configuration Registers" on page 48) are directly mapped into the first 2 KB of this
memory space.
32:11
Base Address 0
R/W
10:4
RSVD
--
3
Prefetchable
RO
2:1
TP
RO
0
IND
RO
00h Base Memory Address: For accessing the configuration registers defined
by the CS4210. A 2 KB address range is used.
0
Reserved
0
Pre-fetchable: 0 indicates the memory is not pre-fetchable.
00
Target Pointer: 00 indicates the base register is 32 bits wide and can be
placed anywhere in the 32-bit memory space.
0
Index: 0 indicates the CS4210 configuration registers are mapped into
memory space of the host system.
Index 14h
Base Address Register 1 (BAR1)
This register specifies the base address of a contiguous memory space in the PCI memory space of the host. This memory space is
assigned to the operational registers defined by National (listed in Section 4.5 "National (NSC) Specific Configuration Registers" on
page 89). These registers are mapped into the first 2 KB of this memory space.
32:11
Base Address 0
R/W
10:4
RSVD
--
3
Prefetchable
RO
2:1
TP
RO
0
IND
RO
00h Base Memory Address: For accessing the vendor defined registers in the
CS4210. A 2 KB address range is used.
0
Reserved
0
Pre-fetchable: 0 indicates the memory is not pre-fetchable.
00
Target Pointer: 00 indicates the base register is 32 bits wide and can be
placed anywhere in the 32-bit memory space.
0
Index: 0 indicates the CS4210 configuration registers are mapped into
memory space of the host system.
Index 18h-2Bh
Reserved
Index 2Ch
Subsystem Vendor Identification Register
15:0
Subsys Vend ID
RO
See Note Subsystem Vendor Identification: This register identifies the vendor of
the subsystem that contains this OpenHCI function. The ID is assigned by
the PCI SIG and is loaded from the serial ROM after power-up reset. This
register can be accessed through NSC register space but cannot be written
from PCI.
Note: The reset value must be set in the serial EEPROM to the vendor identification number assigned by the PCI SIG.
Index 2Eh
Subsystem Identification Register
15:0
Subsys ID
RO
See Note Subsystem Identification: This register identifies the subsystem that con-
tains this OpenHCI function. The ID is assigned by the vendor and is loaded
from the serial ROM after power-up reset. This register can be accessed
through NSC register space but cannot be written from PCI
Note: The reset value must be set in serial EEPROM to a unique number chosen by the user to represent this PCI device implemen-
tation.
Index 30h-33h
Reserved
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