CS4210 Datasheet, PDF(72/102 Page) National Semiconductor (TI)

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

CS4210 Datasheet, PDF (72/102 Pages) National Semiconductor (TI) – IEEE 1394 OHCI Controller

◁

4.4.16.2 Bus Reset

When a bus reset occurs and the busReset interrupt is set

to one, the selfIDComplete (BAR0+Offset 80h[16]) inter-

rupt is simultaneously cleared to 0. The CS4210 prevents

software from clearing the busReset interrupt bit during the

Self-ID phase of bus initialization. Software must take pre-

cautions regarding the asynchronous transmit contexts

before clearing this interrupt. Refer to Section 3.8 "Bus

Resets" on page 30 for further details.

4.4.16.3 IntMask Register

The bits in the IntMask register have the same format as

the IntEvent register, with the addition of masterIntEnable

(bit 31). A one bit in the IntMask register enables the corre-

sponding IntEvent register bit to generate a processor

interrupt. A zero bit in IntMask disables the corresponding

IntEvent register bit from generating a processor interrupt.

A bit is set in the IntMask register by writing a one to the

corresponding bit in the IntMask Set address and cleared

by writing a one to the corresponding bit in the IntMask

Clear address. If masterIntEnable is 0, all interrupts are

disabled regardless of the values of all other bits in the Int-

Mask register. The value of masterIntEnable has no effect

on the value returned by reading the IntEvent Clear; even if

masterIntEnable is 0, reading IntEvent Clear returns

(IntEvent and IntMask) as described earlier in Section

4.4.16 "Interrupts" on page 70.

On a reset, the IntMask.masterIntEnable bit (31) is set to 0

and the value of all other bits is undefined.

1) BAR0+Offset 88h: IntMask Set

2) BAR0+Offset 8Ch: IntMask Clear

Bit

30:27

15:10

Table 4-27. BAR0+Offset 88h (Set) and 8Ch (Clear): IntMask Register

Name

masterIntEnable

Access

RSC

RSVD

phyRegRcvdIntEn

cycleTooLongIntEn

unrecoverableError-

IntEn

cycleInconsis-

tentIntEn

cycleLostIntEn

cycle64SecondsIntEn

cycleSynchIntEn

phyIntEn

RSVD

busResetIntEn

selfIDcompleteIntEn

RSVD

lockRespErrIntEn

postedWriteErrIntEn

isochRxIntEn

isochTxIntEn

RSPktIntEn

RQPktIntEn

ARRSIntEn

ARRQIntEn

respTxCompleteIntEn

reqTxCompleteIntEn

RSC

Reset

Undef

Description

Master Interrupt Enable: If set, external interrupts are generated in

accordance with the IntMask register. If clear, no external interrupts are

generated regardless of the IntMask register settings.

Interrupt Events: A one bit enables the corresponding IntEvent register

bit to generate a processor interrupt. A zero bit disables the corresponding

IntEvent register bit from generating a processor interrupt. See Table 4-26

"BAR0+Offset 80h (Set) and 84h (Clear): IntEvent Register" on page 70.

Undef

www.national.com

Revision 1.0

▷