CS4210 Datasheet, PDF (61/102 Pages) National Semiconductor (TI) – IEEE 1394 OHCI Controller

Register Descriptions (Continued)
4.4.5 Configuration ROM Header Register
The configuration ROM header register (Table 4-14) is a
32-bit number that externally maps to the 1st quadlet of the
1394 configuration ROM (1394 address at offset
FFFF_F000_0400h). This register is written locally at
BAR0+Offset 18h.
4.4.6 Bus Identification Register
The Bus Identification register (Table 4-15) is a 32-bit num-
ber that externally maps to the first quadlet of the
Bus_Info_Block.
Bit
31:24
23:!6
15:0
Table 4-14. BAR0+Offset 18h: ConfigROMhdr Register
Name
info_length
crc_length
Access
RWU
RWU
rom_crc_value
RWU
Reset
00h
00h
0000h
Description
Information Length: IEEE 1394 bus management field. Must be valid at
any time the HCControl.linkEnable bit (BAR0+Offset 50h[17]) is set.
Cyclical Redundancy Check Length: IEEE 1394 bus management field.
Must be valid at any time the HCControl.linkEnable bit (BAR0+Offset
50h[17]) is set.
ROM Cyclical Redundancy Check Value: IEEE 1394 bus management
field. Must be valid at any time the HCControl.linkEnable bit (BAR0+Offset
50h[17]) is set.
Table 4-15. BAR0+Offset 1Ch: Bus Identification Register
Bit
31:0
Name
busID
Access
R
Reset Description
31333934h Bus Identification: This 32-bit number externally maps to the first quadlet of
the Bus_Info_Block. It contains the constant 31333934h which is the ASCII
value for “1394”.
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