MC68HC908BD48 Datasheet, PDF (65/290 Pages) Freescale Semiconductor, Inc – Microcontrollers

Configuration Register (CONFIG)
Functional Description
5.3.2 Configuration Register 1
Address: $001F
Bit 7
6
5
4
3
2
1
Read: 0
0
0
0
SSREC COPRS STOP
Write:
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 5-2. Configuration Register 1 (CONFIG1)
Bit 0
COPD
0
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32
OSCXCLK cycles instead of a 4096-OSCXCLK cycle delay.
1 = Stop mode recovery after 32 OSCXCLK cycles
0 = Stop mode recovery after 4096 OSCXCLKC cycles
NOTE: Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, do not set the SSREC bit.
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS. (See
Section 19. Computer Operating Properly (COP).)
1 = COP timeout period = 2¹³ – 2⁴ CGMXCLK cycles
0 = COP timeout period = 2¹⁸ – 2⁴ CGMXCLK cycles
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See Section 19. Computer
Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
MC68HC908BD48 — Rev. 1.0
MOTOROLA
Configuration Register (CONFIG)
Technical Data
65