MC68HC908BD48 Datasheet, PDF (46/290 Pages) Freescale Semiconductor, Inc – Microcontrollers

Memory Map
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Sync Processor Control ^Read: _LVSIE ^LVSIF _{HPS1 HPS0}
R
$0046
Register 1 Write:
0
(SPCR1) _{Reset: 0}
0
0
0
0
R
ATPOL FSHF
0
0
0
H&V Sync Output Control ^Read: _R
0
0
0
0
HVOCR2 HVOCR1 HVOCR0
$0047
Register Write:
(HVOCR) _{Reset: 0}
0
0
0
0
0
0
0
Read:
$0048
Unimplemented Write:
Reset:
$0049
Read: 0
Port D Configuration
Register (PDCR)
Write:
Reset: 0
IICDATE IICSCLE CLAMPE DDCSCLE DDCDATE USBD–E USBD+E
0
0
0
0
0
0
0
$004A
Multi-Master IIC ^Read: _MMALIF
Master Control Register Write:
(MIMCR) _{Reset: 0}
MMNAKIF
0
MMBB
0
MMAST
0
MMRW
0
MMBR2 MMBR1 MMBR0
0
0
0
$004B
Multi-Master IIC Address ^Read:
Register Write:
(MMADR) _Reset:
MMAD7
1
MMAD6
0
MMAD5
1
MMAD4
0
MMAD3
0
MMAD2
0
MMAD1 MMEXTAD
0
0
$004C
Multi-Master IIC ^Read: _{MMEN MMIEN}
0
0
0
MMTXAK
0
0
Control Register Write:
(MMCR) _{Reset: 0}
0
0
0
0
0
0
0
$004D
Multi-Master IIC ^{Read: MMRXIF MMTXIF MMATCH MMSRW MMRXAK}
0
MMTXBE MMRXBF
Status Register Write: 0
0
(MMSR) _{Reset: 0}
0
0
0
1
0
1
0
$004E
Multi-Master IIC ^Read:
Data Transmit Register Write:
(MMDTR) _Reset:
MMTD7
1
MMTD6
1
MMTD5
1
MMTD4
1
MMTD3
1
MMTD2
1
MMTD1
1
MMTD0
1
$004F
Multi-Master IIC Read: MMRD7
Data Receive Register
(MMDRR)
Write:
Reset: 0
MMRD6
0
MMRD5
0
MMRD4
0
MMRD3
0
MMRD2
0
MMRD1
0
MMRD0
0
= Unimplemented
R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 12)
Technical Data
46
Memory Map
MC68HC908BD48 — Rev. 1.0
MOTOROLA