MC68HC908BD48 Datasheet, PDF (242/290 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output (I/O) Ports
17.6 Port D
Port D is an 7-bit special-function port that shares two of its pins with the
multi-master IIC (MMIIC) module, one of its pins with the sync processor,
two of its pins with the DDC12AB module, and two of its pins with the
USB module.
NOTE: Port pins PTD6–PTD4 and PTD1–PTD0 are not available in a 28-pin
dual in-line package. PTD1–PTD0 are 3.3V pins.
17.6.1 Port D Data Register
The port D data register (PTD) contains a data latch for each of the eight
port D pins.
Address: $0003
Bit 7
Read: 0
Write:
Reset:
Alternate
Function:
6
5
4
3
2
1
PTD6 PTD5 PTD4 PTD3 PTD2 PTD1
Unaffected by reset
IICSDA IICSCL CLAMP DDCSCL DDCSDA D–
Bit 0
PTD0
D+
= Unimplemented
Figure 17-12. Port D Data Register (PTD)
PTD6–PTD0 — Port D Data Bits
These read/write bits are software-programmable. Data direction of
each port D pin is under the control of the corresponding bit in data
direction register D. Reset has no effect on port D data.
IICSDA, IICSCL — Multi-master IIC Data and Clock pins
The PTD6/IICSDA and PTD5/IICSCL pins are multi-master IIC data
and clock pins. When the IICDATE and IICSCLE bits in the port D
configuration register (PDCR) is clear, the PTD6/IICSDA and
PTD5/IICSCL pins are available for general-purpose I/O. See 17.6.3
Port D Options.
Technical Data
242
Input/Output (I/O) Ports
MC68HC908BD48 — Rev. 1.0
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