MC68HC908BD48 Datasheet, PDF (243/290 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output (I/O) Ports
Port D
CLAMP — Sync Processor Clamp pulse output pin
The PTD4/CLAMP pin is the sync processor clamp pulse output pin.
When the CLAMPE bit in the port D configuration register (PDCR) is
clear, the PTD4/CLAMP pin is available for general-purpose I/O. See
17.6.3 Port D Options.
DDCSCL, DDCSDA — DDC12AB Data and Clock pins
The PTD3/DDCSCL and PTD2/DDCSDA pins are DDC12AB clock
and data pins respectively. When the DDCSCLE and DDCDATE bits
in the port D configuration register (PDCR) is clear, the
PTD3/DDCSCL and PTD2/DDCSDA pins are available for general-
purpose I/O. See 17.6.3 Port D Options.
D–, D+ — USB I/O pins
The PTD1/D– and PTD0/D+ pins are the USB port pins. When the
USBD–E and USBD+E bits in the port D configuration register (PDCR)
is clear, the PTD1/D– and PTD0/D+ pins are available for general-
purpose I/O. See 17.6.3 Port D Options.
17.6.2 Data Direction Register D
Data direction register D (DDRD) determines whether each port D pin is
an input or an output. Writing a logic 1 to a DDRD bit enables the output
buffer for the corresponding port D pin; a logic 0 disables the output
buffer.
Address:
Read:
Write:
Reset:
$0007
Bit 7
0
6
5
4
3
2
1
DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1
0
0
0
0
0
0
0
Figure 17-13. Data Direction Register D (DDRD)
Bit 0
DDRD0
0
DDRD6–DDRD0 — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears
DDRD6–DDRD0, configuring all port D pins as inputs.
MC68HC908BD48 — Rev. 1.0
MOTOROLA
Input/Output (I/O) Ports
Technical Data
243