MC68HC908BD48 Datasheet, PDF (212/290 Pages) Freescale Semiconductor, Inc – Microcontrollers

Sync Processor
Table 16-2. Sync Processor I/O Register Summary
Addr. Register Name
Bit 7
6
5
Read:
VSIF
$0040 ^{Sync Processor Control}
VSIE VEDGE
and Status Register Write:
0
(SPCSR)
Reset: 0
0
0
Read: VOF
$0041 ^{Vertical Frequency High}
Register Write:
(VFHR)
Reset: 0
0
CPW1
0
0
CPW0
0
Read: VF7
VF6
VF5
$0042 ^{Vertical Frequency Low}
Register Write:
(VFLR)
Reset: 0
0
0
$0043
Read:
Hsync Frequency High
Register Write:
(HFHR)
Reset:
HFH7
0
HFH6
0
HFH5
0
Read: HOVER
0
0
$0044 ^{Hsync Frequency Low}
Register Write:
(HFLR)
Reset: 0
0
0
$0045
Sync Processor I/O
Control Register
(SPIOCR)
Read:
Write:
Reset:
VSYNCS
0
HSYNCS
0
COINV
0
Read:
$0046 ^{Sync Processor Control}
Register 1 Write:
(SPCR1)
Reset:
LVSIE
0
LVSIF
0
0
HPS1
0
Read:
0
0
$0047
H&V Sync Output
R
Control Register Write:
(HVOCR)
Reset: 0
0
0
= Unimplemented
4
3
2
COMP VINVO HINVO
1
VPOL
Bit 0
HPOL
0
0
0
0
0
VF12 VF11 VF10
VF9
VF8
0
0
0
0
0
VF4
VF3
VF2
VF1
VF0
0
HFH4
0
HFH3
0
HFH2
0
HFH1
0
HFH0
0
HFL4
0
HFL3
0
HFL2
0
HFL1
0
HFL0
0
0
0
0
0
R SOGSEL CLAMPOE BPOR SOUT
0
0
0
0
0
HPS0
R
R
ATPOL FSHF
0
0
0
0
0
0
0
HVOCR2 HVOCR1 HVOCR0
0
0
0
0
0
R = Reserved
Technical Data
212
Sync Processor
MC68HC908BD48 — Rev. 1.0
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