MC68HC908BD48 Datasheet, PDF(274/290 Page) Freescale Semiconductor, Inc – Microcontrollers

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MC68HC908BD48 Datasheet, PDF (274/290 Pages) Freescale Semiconductor, Inc – Microcontrollers

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Electrical Speciï¬cations

21.6 DC Electrical Characteristics

Characteristic

Symbol

Min

Typ(2)

Max

Unit

Output High Voltage

(ILOAD = â2.0mA) All I/O Pins

Output Low Voltage

(ILOAD = 1.6mA) All I/O Pins

Input High Voltage

All ports, IRQ, RST, OSC1

VOH

VDD â 0.8

â

VOL

â

â

VIH

0.7 Ã VDD

â

â

V

0.4

V

VDD

V

Input Low Voltage

All ports, IRQ, RST, OSC1

VIL

VSS

â

0.2 Ã VDD

V

VDD Supply Current

Run, USB active

Run, USB suspended(3)

Wait (4)

Stop(5) 0Â°C to 85Â°C

â

10

15

mA

IDD

â

8

12

mA

â

4

8

mA

â

2

5

mA

I/O Ports Hi-Z Leakage Current

Input Current

Capacitance

Ports (as Input or Output)

POR ReArm Voltage(6)

POR Rise Time Ramp Rate(7)

Monitor Mode Entry Voltage

Pull-up Resistor

RST, IRQ

IIL

â

â

IIN

â

â

COUT

â

â

CIN

â

â

VPOR

0

â

RPOR

0.035

â

VTST

VDD + 2.5

RPU

20

45

Â± 10

ÂµA

Â±1

ÂµA

12

8

pF

100

mV

â

V/ms

9

V

65

kâ¦

Low-Voltage Inhibit, trip falling voltage

VTRIPF

3.5

3.8

4.5

V

Low-Voltage Inhibit, trip rising voltage

VTRIPR

3.5

4.0

4.5

V

Low-Voltage Inhibit Reset/Recover Hysteresis

VHYS

â

200

â

mV

NOTES:

1. VDD = 5.0 Vdc Â± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.

2. Typical values reflect average measurements at midpoint of voltage range, 25 Â°C only.

3. Run (operating) IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on

all outputs. CL = 15 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules

enabled.

4. Wait IDD measured using external square wave clock source (fOSCXCLK = 24MHz); all inputs 0.2 V from rail; no dc loads; less than 100

pF on all outputs. CL = 15pF on OSC2; USB in suspend mode, 15 Kâ¦ Â± 5% termination resistors on D+ and Dâ pins; all ports config-

ured as inputs; OSC2 capacitance linearly affects wait IDD.

5. STOP IDD measured with USB in suspend mode, OSC1 grounded, 1.5 Kâ¦ Â± 1% pull-up resistor on D+ pin and 15 Kâ¦ Â± 1% pull-down

resistors on D+ and Dâ pins, no port pins sourcing current.

6. Maximum is highest voltage that POR is guaranteed.

7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is

reached.

Technical Data

274

Electrical Specifications

MC68HC908BD48 â Rev. 1.0

MOTOROLA

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