MC68HC908BD48 Datasheet, PDF (19/290 Pages) Freescale Semiconductor, Inc – Microcontrollers

List of Figures
Figure
Title
Page
12-2 ADC Status and Control Register (ADSCR) . . . . . . . . . . . . . . 158
12-3 ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12-4 ADC Input Clock Register (ADICLK) . . . . . . . . . . . . . . . . . . . 161
13-1
13-2
13-3
13-4
13-5
13-6
13-7
13-8
13-9
USB Address Register (UADR) . . . . . . . . . . . . . . . . . . . . . . . 166
USB Interrupt Register (UINTR) . . . . . . . . . . . . . . . . . . . . . . . 166
USB Interrupt Register 1 (UIR1) . . . . . . . . . . . . . . . . . . . . . . . 169
USB Control Register 0 (UCR0) . . . . . . . . . . . . . . . . . . . . . . . 171
USB Control Register 1 (UCR1) . . . . . . . . . . . . . . . . . . . . . . . 172
USB Control Register 2 (UCR2) . . . . . . . . . . . . . . . . . . . . . . . 174
USB Status Register (USR) . . . . . . . . . . . . . . . . . . . . . . . . . . 175
USB Endpoint 0 Data Registers 0 to 7 (UD0R0–UD0R7) . . . 177
USB Endpoint 1 Data Registers 0 to 7 (UD1R0–UD1R7) . . . 177
14-1
14-2
14-3
14-4
14-5
14-6
14-7
Multi-Master IIC Address Register (MMADR). . . . . . . . . . . . . 182
Multi-Master IIC Control Register (MMCR). . . . . . . . . . . . . . . 183
Multi-Master IIC Master Control Register (MIMCR) . . . . . . . . 184
Multi-Master IIC Status Register (MMSR) . . . . . . . . . . . . . . . 186
Multi-Master IIC Data Transmit Register (MMDTR) . . . . . . . . 188
Multi-Master IIC Data Receive Register (MMDRR) . . . . . . . . 189
Data Transfer Sequences for Master/Slave
Transmit/Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 191
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
DDC Address Register (DADR) . . . . . . . . . . . . . . . . . . . . . . . 196
DDC2 Address Register (D2ADR) . . . . . . . . . . . . . . . . . . . . . 197
DDC Control Register (DCR) . . . . . . . . . . . . . . . . . . . . . . . . . 198
DDC Master Control Register (DMCR). . . . . . . . . . . . . . . . . . 199
DDC Status Register (DSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 202
DDC Data Transmit Register (DDTR). . . . . . . . . . . . . . . . . . . 204
DDC Data Receive Register (DDRR) . . . . . . . . . . . . . . . . . . . 205
Data Transfer Sequences for Master/Slave
Transmit/Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 207
16-1 Sync Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 213
16-2 Clamp Pulse Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 216
16-3 Sync Processor Control & Status Register (SPCSR) . . . . . . . 217
MC68HC908BD48 — Rev. 1.0
MOTOROLA
List of Figures
Technical Data
19