MC68HC908BD48 Datasheet, PDF (215/290 Pages) Freescale Semiconductor, Inc – Microcontrollers

Sync Processor
Functional Blocks
16.5.2 Sync Signal Counters
There are two counters: a 13-bit horizontal frequency counter to count
the number of horizontal sync pulses within a 32ms or 8ms period; and
a 13-bit vertical frequency counter to count the number of system clock
cycles between two vertical sync pulses. These two data can be read by
the CPU to check the signal frequencies and to determine the video
mode.
The 13-bit vertical frequency register encompasses vertical frequency
range from approximately 15Hz to 128kHz. Due to the asynchronous
timing between the incoming VSYNC signal and internal system clock,
there will be ±1 count error on reading the Vertical Frequency
Registers (VFRs) for the same vertical frequency.
The horizontal counter counts the pulses on HSYNC pin input, and is
uploaded to the Hsync Frequency Registers (HFRs) every 32.768ms
or 8.192ms.
16.5.3 Polarity Controlled HSYNCO and VSYNCO Outputs
The processed sync signals are output on HSYNCO and VSYNCO when
the corresponding bits in Configuration Register 0 ($001D) are set. The
signal to these output pins depend on SOUT and COMP bits (see Table
16-3), with polarity controlled by ATPOL, HINVO, and VINVO bits as
shown in Table 16-4.
SOUT
1
0
0
Table 16-3. Sync Output Control
COMP
X
0
1
Sync Outputs:
VSYNCO and HSYNCO
Free-running pulse with negative polarity
Sync outputs follow sync inputs VSYNC and HSYNC
respectively, with polarity correction shown in Table 16-4.
HSYNCO follows the composite sync input and VSYNCO
is the extracted Vsync (3 to 14µs delay to composite input),
with polarity correction shown in Table 16-4.
MC68HC908BD48 — Rev. 1.0
MOTOROLA
Sync Processor
Technical Data
215