MC68HC908BD48 Datasheet, PDF (184/290 Pages) Freescale Semiconductor, Inc – Microcontrollers

Multi-Master IIC Interface (MMIIC)
14.5.3 Multi-Master IIC Master Control Register (MIMCR)
Address: $004A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
MMALIF MMNAKIF MMBB
Write:
MMAST
MMRW
MMBR2 MMBR1 MMBR0
Reset: 0
0
0
0
0
0
0
0
Figure 14-3. Multi-Master IIC Master Control Register (MIMCR)
MMALIF — Multi-Master Arbitration Lost Interrupt Flag
The flag is set when software attempt to set MMAST but the MMBB
has been set by detecting the start condition on the lines or when the
MMIIC is transmitting a "1" to SDA line but detected a "0" from SDA
line in master mode – an arbitration loss. This bit generates an
interrupt request to the CPU if the MMIEN bit in MMCR is also set.
This bit is cleared by writing "0" to it or by reset.
1 = Lost arbitration in master mode
0 = No arbitration lost
MMNAKIF — No Acknowledge Interrupt Flag
The flag is only set in master mode (MMAST = 1) when there is no
acknowledge bit detected after one data byte or calling address is
transferred. This flag also clears MMAST. MMNAKIF generates an
interrupt request to CPU if the MMIEN bit in MMCR is also set. This
bit is cleared by writing "0" to it or by reset.
1 = No acknowledge bit detected
0 = Acknowledge bit detected
MMBB — Bus Busy Flag
This flag is set after a start condition is detected (bus busy), and is
cleared when a stop condition (bus idle) is detected or the MMIIC is
disabled. Reset clears this bit.
1 = Start condition detected
0 = Stop condition detected or MMIIC is disabled
Technical Data
184
Multi-Master IIC Interface (MMIIC)
MC68HC908BD48 — Rev. 1.0
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