MC68HC908BD48 Datasheet, PDF (216/290 Pages) Freescale Semiconductor, Inc – Microcontrollers

Sync Processor
ATPOL
X
0
0
1
1
Table 16-4. Sync Output Polarity
SOUT
1
0
0
0
0
VINVO
or
HINVO
X
0
1
0
1
Sync Outputs:
VSYNCO/HSYNCO
Free-running pulse with negative polarity
Same polarity as sync input
Inverted polarity of sync input
Negative polarity sync output
Positive polarity sync output
When the SOUT bit is set, the HSYNCO output is a free-running pulse
with 2µs width. Both HSYNCO and VSYNCO outputs are negative
polarity, with frequencies selected by the H & V Sync Output Control
Register (HVOCR).
16.5.4 Clamp Pulse Output
When the CLAMPOE bit in SPIOCR is set to "1", a clamp signal is output
on the CLAMP pin. This clamp pulse is triggered either on the leading
edge or the trailing edge of HSYNC, controlled by BPOR bit, with the
polarity controlled by the COINV bit. See Figure 16-2 . Clamp Pulse
Output Timing.
HSYNC
(HPOL = 1)
CLAMP
(BPOR = 0)
Pulse width = 0.33~2.1µs
CLAMP
(BPOR = 1)
Pulse width = 0.33~2.1µs
HSYNC
(HPOL = 0)
CLAMP
(BPOR = 0)
Pulse width = 0.33~2.1µs
CLAMP
(BPOR = 1)
Pulse width = 0.33~2.1µs
Figure 16-2. Clamp Pulse Output Timing
Technical Data
216
Sync Processor
MC68HC908BD48 — Rev. 1.0
MOTOROLA