MC68HC908BD48 Datasheet, PDF (169/290 Pages) Freescale Semiconductor, Inc – Microcontrollers

Universal Serial Bus Module (USB)
Registers
13.5.3 USB Interrupt Register 1 (UIR1)
Address: $002E
Bit 7
6
5
4
3
2
1
Bit 0
Read: TXD1F
Write: 0
RESUMF 0
0
TXD1IE
0 RESUMFR TBEFR
0
0
0
RBFFR TXD1FR EOPFR
Reset: 0
0
0
0
0
0
0
0
Figure 13-3. USB Interrupt Register 1 (UIR1)
TXD1F — Endpoint 1/2 Data Buffer Transmit Flag
The flag is set after the data stored in endpoint 1/2 transmit buffer has
been sent and ACK handshake packet from host is received.
Software must clear this flag by writing a logic 1 to TXD1FR bit after
the data is ready in the transmit buffer to enable the next data packet
transmission when TX1E is enabled. Reset clears this bit.
1 = Transmit on endpoint 1/2 has occurred
0 = Transmit on endpoint 1/2 has not occurred
TXD1IE — Transmit Buffer Interrupt Enable
When this bit is set, the TXD1F flag is enabled to generate an interrupt
request to the CPU. When TXD1IE is cleared, the TXD1F flag is
prevented from generating an interrupt request to the CPU. Reset
clears this bit.
1 = TXD1F bit set will generate interrupt request to CPU
0 = TXD1F bit set does not generate interrupt request to CPU
RESUMF — Resume Flag
This flag is set if the transaction from idle state to non-idle state is
detected while in suspend mode (SUSPND = 1). An interrupt will be
generated to wake up CPU to indicate a resume signalling from host
and software will clear SUSPND bit and exit from suspend mode.
USB reset signals cannot be detected while in suspend mode until
SUSPND bit is cleared. The RESUMF interrupt service routine is
generated by SE0 to wake up the USB module. This bit can be
cleared by writing "1" to RESUMFR bit. Reset clears this bit.
1 = USB bus activity detected while in suspend mode
0 = If in suspend mode, no USB bus activity has been detected
MC68HC908BD48 — Rev. 1.0
MOTOROLA
Universal Serial Bus Module (USB)
Technical Data
169