MC68HC908BD48 Datasheet, PDF (45/290 Pages) Freescale Semiconductor, Inc – Microcontrollers

Memory Map
Input/Output (I/O) Section
Addr.
$003C
$003D
$003E
$003F
$0040
$0041
$0042
$0043
$0044
$0045
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
USB Endpoint 1/2 Data
Register 4 (UD1R4)
Write:
UE1TD47
UE1TD46
UE1TD45
UE1TD44
UE1TD43
UE1TD42
UE1TD41
UE1TD40
Reset:
Indeterminate after reset
Read:
USB Endpoint 1/2 Data
Register 5 (UD1R5)
Write:
UE1TD57
UE1TD56
UE1TD55
UE1TD54
UE1TD53
UE1TD52
UE1TD51
UE1TD50
Reset:
Indeterminate after reset
Read:
USB Endpoint 1/2 Data
Register 6 (UD1R6)
Write:
UE1TD67
UE1TD66
UE1TD65
UE1TD64
UE1TD63
UE1TD62
UE1TD61
UE1TD60
Reset:
Indeterminate after reset
Read:
USB Endpoint 1/2 Data
Register 7 (UD1R7)
Write:
UE1TD77
UE1TD76
UE1TD75
UE1TD74
UE1TD73
UE1TD72
UE1TD71
UE1TD70
Reset:
Indeterminate after reset
Sync Processor Control ^Read: _{VSIE VEDGE} ^VSIF
and Status Register Write:
0
(SPCSR) _{Reset: 0}
0
0
VPOL
COMP VINVO HINVO
0
0
0
0
HPOL
0
Vertical Frequency High ^{Read: VOF}
0
0
VF12 VF11 VF10
VF9
VF8
Register Write:
CPW1 CPW0
(VFHR) _{Reset: 0}
0
0
0
0
0
0
0
Vertical Frequency Low ^{Read: VF7}
VF6
VF5
VF4
VF3
VF2
VF1
VF0
Register Write:
(VFLR) _{Reset: 0}
0
0
0
0
0
0
0
Hsync Frequency High ^Read:
Register Write:
(HFHR) _Reset:
HFH7
0
HFH6
0
HFH5
0
HFH4
0
HFH3
0
HFH2
0
HFH1
0
HFH0
0
Hsync Frequency Low ^{Read: HOVER}
0
Register Write:
(HFLR) _{Reset: 0}
0
0
HFL4 HFL3 HFL2 HFL1 HFL0
0
0
0
0
0
0
Sync Processor I/O ^{Read: VSYNCS}
Control Register Write:
(SPIOCR) _{Reset: 0}
HSYNCS
0
COINV
0
R SOGSEL CLAMPOE BPOR SOUT
0
0
0
0
0
= Unimplemented
R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 12)
MC68HC908BD48 — Rev. 1.0
MOTOROLA
Memory Map
Technical Data
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