MC68HC908BD48 Datasheet, PDF (245/290 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output (I/O) Ports
Port D
17.6.3 Port D Options
The port D configuration register (PDCR) selects the port D pins for
module function or as standard I/O function.
Address: $0049
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
Write:
IICDATE IICSCLE CLAMPE DDCSCLE DDCDATE USBD–E USBD+E
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 17-15. Port D Configuration Register (PDCR)
IICDATE — MMIIC Data Pin Enable
This bit is set to configure the PTD6/IICSDA pin for IICSDA function.
Reset clears this bit.
1 = PTD6/IICSDA pin configured as IICSDA pin
0 = PTD6/IICSDA pin configured as standard I/O pin
IICSCLE — MMIIC Clock Pin Enable
This bit is set to configure the PTD5/IICSCL pin for IICSCL function.
Reset clears this bit.
1 = PTD5/IICSCL pin configured as IICSCL pin
0 = PTD5/IICSCL pin configured as standard I/O pin
CLAMP — CLAMP Pin Enable
This bit is set to configure the PTD4/CLAMP pin for sync processor
clamp pulse output. Reset clears this bit.
1 = PTD4/CLAMP pin configured as CLAMP pin
0 = PTD4/CLAMP pin configured as standard I/O pin
DDCSCLE — DDC Clock Pin Enable
This bit is set to configure the PTD3/DDCSCL pin for DDCSCL
function. Reset clears this bit.
1 = PTD3/DDCSCL pin configured as DDCSCL pin
0 = PTD3/DDCSCL pin configured as standard I/O port
MC68HC908BD48 — Rev. 1.0
MOTOROLA
Input/Output (I/O) Ports
Technical Data
245