MC68HC908BD48 Datasheet, PDF (248/290 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output (I/O) Ports
SOG/TCH0 — SOG Output or TCH0 Input
The PTE0/SOG/TCH0 pin is the SOG input for the sync processor or
the input capture of the TIM channel 0. See 17.7.3 Port E Options.
17.7.2 Data Direction Register E
Data direction register E (DDRE) determines whether each port E pin is
an input or an output. Writing a logic 1 to a DDRE bit enables the output
buffer for the corresponding port E pin; a logic 0 disables the output
buffer.
Address: $000C
Bit 7
6
5
4
3
2
1
Read: 0
0
0
0
0
DDRE2 DDRE1
Write:
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 17-17. Data Direction Register E (DDRE)
Bit 0
DDRE0
0
DDRE2–DDRE0 — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears
DDRE2–DDRE0, configuring all port E pins as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE: Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
NOTE: For those devices packaged in a 28-pin dual in-line package, set DDRE0
to a 1 to configure PTE0 as an output.
Figure 17-18 shows the port E I/O logic.
Technical Data
248
Input/Output (I/O) Ports
MC68HC908BD48 — Rev. 1.0
MOTOROLA