MC68HC908BD48 Datasheet, PDF (223/290 Pages) Freescale Semiconductor, Inc – Microcontrollers

Sync Processor
Registers
CPW[1:0] — Clamp Pulse Width
The CPW1 and CPW0 bits are used to select the output clamp pulse
width. Reset clears these bits, selecting a default clamp pulse width
between 0.33µs and 0.375µs. These bits always read as Zeros.
Table 16-7. Clamp Pulse Width
CPW1
0
0
1
1
CPW0
0
1
0
1
Clamp Pulse Width
0.33µs to 0.375µs
0.5µs to 0.542µs
0.75µs to 0.792µs
2µs to 2.042µs
16.6.4 Hsync Frequency Registers (HFRs)
This register pair contains the 13-bit Hsync frequency count value and
an overflow bit.
Address: $0043
Bit 7
6
5
4
3
2
1
Read: HFH7 HFH6 HFH5 HFH4 HFH3 HFH2 HFH1
Write:
Reset: 0
0
0
0
0
0
0
Figure 16-7. Hsync Frequency High Register
Bit 0
HFH0
0
Address: $0044
Bit 7
6
5
4
3
2
1
Bit 0
Read: HOVER
0
0
HFL4 HFL3 HFL2 HFL1 HFL0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 16-8. Hsync Frequency Low Register
MC68HC908BD48 — Rev. 1.0
MOTOROLA
Sync Processor
Technical Data
223