|
MC68HC908BD48 Datasheet, PDF (238/290 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
|
◁ |
Input/Output (I/O) Ports
When bit DDRBx is a logic 1, reading address $0001 reads the PTBx
data latch. When bit DDRBx is a logic 0, reading address $0001 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 17-4 summarizes
the operation of the port B pins.
Table 17-4. Port B Pin Functions
DDRB Bit
PTB Bit
I/O Pin Mode
0
X(1)
Input, Hi-Z(2)
Accesses
to DDRB
Read/Write
DDRB7âDDRB0
1
X
Output
DDRB7âDDRB0
Notes:
1. X = Donât care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
Accesses to PTB
Read
Pin
PTB7âPTB0
Write
PTB7âPTB0(3)
PTB7âPTB0
17.4.3 Port B Options
The PWM control register 1 (PWMCR1) selects the port B pins for PWM
function or as standard I/O function. See 11.4.2 PWM Control
Registers 1 and 2 (PWMCR1:PWMCR2).
Address: $0028
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PWM7E PWM6E PWM5E PWM4E PWM3E PWM2E PWM1E PWM0E
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 17-8. PWM Control Register 1 (PWMCR1)
PWM7EâPWM0E â PWM Output Enable 7â0
Setting a bit to "1" will configure the corresponding PTBx/PWMx pin
for PWM output function. Reset clears these bits.
1 = PTBx/PWMx pin configured as PWMx output pin
0 = PTBx/PWMx pin configured as standard I/O pin
Technical Data
238
Input/Output (I/O) Ports
MC68HC908BD48 â Rev. 1.0
MOTOROLA
|
▷ |