MC68HC908BD48 Datasheet, PDF (180/290 Pages) Freescale Semiconductor, Inc – Microcontrollers

Multi-Master IIC Interface (MMIIC)
This Multi-master IIC module uses the IICSCL clock line and the IICSDA
data line to communicate with external DDC host or IIC interface. These
two pins are shared with port pins PTD5 and PTD6 respectively. The
outputs of IICSDA and IICSCL pins are open-drain type — no clamping
diode is connected between the pin and internal V_DD. The maximum
data rate typically is 750k-bps. The maximum communication length and
the number of devices that can be connected are limited by a maximum
bus capacitance of 400pF.
14.3 Features
• Compatibility with multi-master IIC bus standard
• Software controllable acknowledge bit generation
• Interrupt driven byte by byte data transfer
• Calling address identification interrupt
• Auto detection of R/W bit and switching of transmit or receive
mode
• Detection of START, repeated START, and STOP signals
• Auto generation of START and STOP condition in master mode
• Arbitration loss detection and No-ACK awareness in master mode
• 8 selectable baud rate master clocks
• Automatic recognition of the received acknowledge bit
14.4 I/O Pins
The MMIIC module uses two I/O pins, shared with standard port I/O pins.
The full name of the MMIIC I/O pins are listed in Table 14-1. The generic
pin name appear in the text that follows.
MMIIC
Generic Pin Names:
SDA
SCL
Table 14-1. Pin Name Conventions
Full MCU Pin Names:
PTD6/IICSDA
PTD5/IICSCL
Pin Selected for
IIC Function By:
IICDATE bit in PDCR ($0049)
IICSCLE bit in PDCR ($0049)
Technical Data
180
Multi-Master IIC Interface (MMIIC)
MC68HC908BD48 — Rev. 1.0
MOTOROLA