MC68HC908BD48 Datasheet, PDF (64/290 Pages) Freescale Semiconductor, Inc – Microcontrollers

Configuration Register (CONFIG)
registers are located at $001D and $001F. The configuration register
may be read at anytime.
5.3.1 Configuration Register 0
Address: $001D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
HSYNCOE VSYNCOE SOGE
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 5-1. Configuration Register 0 (CONFIG0)
HSYNCOE — VSYNCO Enable
This bit is set to configure the PTE1/HSYNCO pin for HSYNCO output
function. Reset clears this bit.
1 = PTE1/HSYNCO pin configured as HSYNCO pin
0 = PTE1/HSYNCO pin configured as standard I/O pin
VSYNCOE — VSYNCO Enable
This bit is set to configure the PTE2/VSYNCO pin for VSYNCO output
function. Reset clears this bit.
1 = PTE2/VSYNCO pin configured as VSYNCO pin
0 = PTE2/VSYNCO pin configured as standard I/O pin
SOGE — SOG Enable
This bit is set to configure the PTE0/SOG/TCH0 pin for SOG output
function. Reset clears this bit.
1 = PTE0/SOG/TCH0 pin configured as SOG pin
0 = PTE0/SOG/TCH0 pin configured as standard I/O or TCH0 pin.
TCH0 function is configured by ELS0B and ELS0A bits in
TSC0 (bits 3 and 2 in $0010). (See 10.10.4 TIM Channel
Status and Control Registers (TSC0:TSC1).)
Technical Data
64
Configuration Register (CONFIG)
MC68HC908BD48 — Rev. 1.0
MOTOROLA