MC68HC908BD48 Datasheet, PDF (186/290 Pages) Freescale Semiconductor, Inc – Microcontrollers

Multi-Master IIC Interface (MMIIC)
Table 14-3. Baud Rate Select
MMBR2 MMBR1 MMBR0
Baud Rate
0
0
0
750 k
0
0
1
375 k
0
1
0
187.5 k
0
1
1
93.75 k
1
0
0
46.875 k
1
0
1
23.437 k
1
1
0
11.719 k
1
1
1
5.859 k
NOTE:
CPU bus clock is external clock ÷ 4 = 6MHz
14.5.4 Multi-Master IIC Status Register (MMSR)
Address: $004D
Bit 7
6
5
4
3
2
1
Bit 0
Read: MMRXIF MMTXIF MMATCH MMSRW MMRXAK 0 MMTXBE MMRXBF
Write: 0
0
Reset: 0
0
0
0
1
0
1
0
= Unimplemented
Figure 14-4. Multi-Master IIC Status Register (MMSR)
MMRXIF — Multi-Master IIC Receive Interrupt Flag
This flag is set after the data receive register (MMDRR) is loaded with
a new received data. Once the MMDRR is loaded with received data,
no more received data can be loaded to the MMDRR register until the
CPU reads the data from the MMDRR to clear MMRXBF flag.
MMRXIF generates an interrupt request to CPU if the MMIEN bit in
MMCR is also set. This bit is cleared by writing "0" to it or by reset; or
when the MMEN = 0.
1 = New data in data receive register (MMDRR)
0 = No data received
Technical Data
186
Multi-Master IIC Interface (MMIIC)
MC68HC908BD48 — Rev. 1.0
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