MC68HC908BD48 Datasheet, PDF (244/290 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output (I/O) Ports
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE: Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
NOTE: For those devices packaged in a 28-pin dual in-line package, set
DDRD6, 5, 4, 1 and 0 to a 1 to configure PTD6, 5, 4, 1 and 0 as outputs.
Figure 17-14 shows the port D I/O logic.
READ DDRD ($0007)
WRITE DDRD ($0007)
RESET
WRITE PTD ($0003)
DDRDx
PTDx
PTDx
READ PTD ($0003)
Figure 17-14. Port D I/O Circuit
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx
data latch. When bit DDRDx is a logic 0, reading address $0003 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 17-6 summarizes
the operation of the port D pins.
Table 17-6. Port D Pin Functions
PTDPUE Bit
0
DDRD Bit
0
PTD Bit
X
I/O Pin Mode
Input, Hi-Z⁽²⁾
Accesses to DDRD
Read/Write
DDRD7–DDRD0
Accesses to PTD
Read
Pin
Write
PTD7–PTD0⁽³⁾
X
1
X
Output
DDRD7–DDRD0 PTD7–PTD0 PTD7–PTD0
Notes:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
Technical Data
244
Input/Output (I/O) Ports
MC68HC908BD48 — Rev. 1.0
MOTOROLA