MC68HC908BD48 Datasheet, PDF (220/290 Pages) Freescale Semiconductor, Inc – Microcontrollers

Sync Processor
COINV — Clamp Output Invert
This bit is set to invert the clamp pulse output to negative. Reset
clears this bit.
1 = clamp output is set for negative pulses
0 = clamp output is set for positive pulses
SOGSEL — SOG Select
This bit selects either the HSYNC pin or SOG pin as the composite
sync signal input pin. Reset clears this bit.
1 = SOG pin is used as the composite sync input
0 = HSYNC pin is used as the composite sync input
CLAMPOE — Clamp Output Enable
This bit is set to enable the clamp pulse output circuitry. Reset clears
this bit.
1 = Clamp pulse circuit enabled
0 = Clamp pulse circuit disabled
BPOR — Back Porch
This bit defines the triggering edge of the clamp pulse output relative
to the HSYNC input. Reset clears this bit.
1 = Clamp pulse is generated on the trailing edge of HSYNC
0 = Clamp pulse is generated on the leading edge of HSYNC
SOUT — Sync Output Enable
This bit will select the output signals for the VSYNCO and HSYNCO
pins. Reset clears this bit.
1 = VSYNCO and HSYNCO outputs are internally generated
free-running sync pulses with frequencies determined by
HVCOR[2:0] bits in HVCOR.
0 = VSYNCO and HSYNCO outputs are processed VSYNC and
HSYNC inputs respectively
Technical Data
220
Sync Processor
MC68HC908BD48 — Rev. 1.0
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