PIC18F-LF1XK50 Datasheet, PDF (97/420 Pages) Microchip Technology – 20-Pin USB Flash Microcontrollers

PIC18F/LF1XK50
TABLE 9-14: PORTC I/O SUMMARY (CONTINUED)
Pin
Function
TRIS
Setting
I/O
I/O
Type
Description
RC5/CCP1/P1A/
T0CKI
RC5
0
O
DIG LATC<5> data output.
1
I
ST PORTC<5> data input.
CCP1
0
O
DIG ECCP1 compare or PWM output; takes priority over port data.
1
I
ST ECCP1 capture input.
P1A
0
0
DIG ECCP1 Enhanced PWM output, channel A. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data
T0CKI
1
I
ST Timer0 counter input.
RC6/AN8/SS/
T13CKI/T1OSCI
RC6
0
O
DIG LATC<6> data output.
1
I
ST PORTC<6> data input.
AN8
1
I
ANA A/D input channel 8.
SS
1
I
TTL Slave select input for SSP (MSSP module)
T13CKI
1
I
ST Timer1 and Timer3 counter input.
T1OSCI
x
O
ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled.
Disables digital I/O.
RC7/AN9/SDO/
T1OSCO
RC7
0
O
DIG LATC<7> data output.
1
I
ST PORTC<7> data input.
AN9
1
I
ANA A/D input channel 9.
SDO
0
I
DIG SPI data output (MSSP module); takes priority over port data.
T1OSCO ^x
O
ANA Timer1 oscillator output; enabled when Timer1 oscillator enabled.
Disables digital I/O.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
I²C/SMB = I²C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TABLE 9-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
288
LATC
LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0
288
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 ²⁸⁸
ANSEL
ANS7
ANS6
ANS5
ANS4 ANS3
—
—
—
288
ANSELH
—
—
—
—
ANS11 ANS10 ANS9 ANS8
288
T1CON
RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 286
T3CON
RD16
—
T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 287
SSPCON1 WCOL SSPOV SSPEN
CKP SSPM3 SSPM2 SSPM1 SSPM0 286
CCP1CON P1M1
P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 287
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 287
PSTRCON
—
—
— STRSYNC STRD STRC STRB STRA
287
SLRCON
—
—
—
—
—
SLRC SLRB SLRA
288
REFCON1 D1EN D1LPS DAC1OE
---
D1PSS1 D1PSS0 ---
D1NSS 287
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF
285
INTCON2 RABPU INTEDG0 INTEDG1 INTEDG2
—
TMR0IP
—
RABIP
285
INTCON3 INT2IP INT1IP
—
INT2IE INT1IE
—
INT2IF INT1IF 285
 2010 Microchip Technology Inc.
Preliminary
DS41350E-page 97