PIC18F-LF1XK50 Datasheet, PDF (80/420 Pages) Microchip Technology – 20-Pin USB Flash Microcontrollers

PIC18F/LF1XK50
7.9 INTn Pin Interrupts
External interrupts on the RC0/INT0, RC1/INT1 and
RC2/INT2 pins are edge-triggered. If the
corresponding INTEDGx bit in the INTCON2 register is
set (= 1), the interrupt is triggered by a rising edge; if
the bit is clear, the trigger is on the falling edge. When
a valid edge appears on the RCx/INTx pin, the
corresponding flag bit, INTxF, is set. This interrupt can
be disabled by clearing the corresponding enable bit,
INTxE. Flag bit, INTxF, must be cleared by software in
the Interrupt Service Routine before re-enabling the
interrupt.
All external interrupts (INT0, INT1 and INT2) can wake-
up the processor from Idle or Sleep modes if bit INTxE
was set prior to going into those modes. If the Global
Interrupt Enable bit, GIE, is set, the processor will
branch to the interrupt vector following wake-up.
Interrupt priority for INT1 and INT2 is determined by
the value contained in the interrupt priority bits,
INT1IP and INT2IP of the INTCON3 register. There is
no priority bit associated with INT0. It is always a high
priority interrupt source.
7.10 TMR0 Interrupt
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh  00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L regis-
ter pair (FFFFh 0000h) will set TMR0IF. The interrupt
can be enabled/disabled by setting/clearing enable bit,
TMR0IE of the INTCON register. Interrupt priority for
Timer0 is determined by the value contained in the
interrupt priority bit, TMR0IP of the INTCON2 register.
See Section 10.0 “Timer0 Module” for further details
on the Timer0 module.
7.11 PORTA and PORTB Interrupt-on-
Change
An input change on PORTA or PORTB sets flag bit,
RABIF of the INTCON register. The interrupt can be
enabled/disabled by setting/clearing enable bit, RABIE
of the INTCON register. Pins must also be individually
enabled with the IOCA and IOCB register. Interrupt
priority for PORTA and PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RABIP of the INTCON2 register.
7.12 Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the fast return stack. If a fast
return from interrupt is not used (see Section 3.3
“Data Memory Organization”), the user may need to
save the WREG, STATUS and BSR registers on entry
to the Interrupt Service Routine. Depending on the
user’s application, other registers may also need to be
saved. Example 7-1 saves and restores the WREG,
STATUS and BSR registers during an Interrupt Service
Routine.
EXAMPLE 7-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF
W_TEMP
MOVFF
STATUS, STATUS_TEMP
MOVFF
BSR, BSR_TEMP
;
; USER ISR CODE
;
MOVFF
BSR_TEMP, BSR
MOVF
W_TEMP, W
MOVFF
STATUS_TEMP, STATUS
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
; Restore BSR
; Restore WREG
; Restore STATUS
DS41350E-page 80
Preliminary
 2010 Microchip Technology Inc.