PIC18F-LF1XK50 Datasheet, PDF (87/420 Pages) Microchip Technology – 20-Pin USB Flash Microcontrollers

PIC18F/LF1XK50
TABLE 9-1: PORTA I/O SUMMARY
Pin
Function
TRIS
Setting
I/O
I/O
Type
Description
RA0/IOCA0/D+/
PGD
RA0
IOCA0
D+
PGD
RA1/IOCA1/D-/
PGC
RA1
IOCA1
D-
PGC
RA3/IOCA3/MCLR/
VPP
RA3
IOCA3
—⁽¹⁾
—⁽¹⁾
—⁽¹⁾
—⁽¹⁾
—⁽¹⁾
—⁽¹⁾
—⁽¹⁾
—⁽¹⁾
—⁽¹⁾
—⁽¹⁾
—⁽¹⁾
—⁽¹⁾
—⁽²⁾
—⁽¹⁾
I
TTL PORTA<0> data input; disabled when USB enabled.
I
TTL Interrupt-on-pin change; disabled when USB enabled.
I XCVR USB bus differential plus line input (internal transceiver).
O XCVR USB bus differential plus line output (internal transceiver).
O DIG Serial execution data output for ICSP™.
I
ST Serial execution data input for ICSP™.
I
TTL PORTA<1> data input; disabled when USB enabled.
I
TTL Interrupt-on-pin change; disabled when USB enabled.
I XCVR USB bus differential minus line input (internal transceiver).
O XCVR USB bus differential minus line output (internal transceiver).
O DIG Serial execution clock output for ICSP™.
I
ST Serial execution clock input for ICSP™.
I
ST PORTA<3> data input; enabled when MCLRE Configuration bit is
clear; Programmable weak pull-up.
I
TTL Interrupt-on-pin change
MCLR
—
I
ST External Master Clear input; enabled when MCLRE Configuration bit is
set.
VPP
—
I ANA High-voltage detection; used for ICSP™ mode entry detection. Always
available, regardless of pin mode.
RA4/IOCA4/AN3/
OSC2/CLKOUT
RA4
0
O DIG LATA<4> data output. Enabled in RCIO, INTIO2 and ECIO modes only.
1
I
TTL PORTA<4> data input; Programmable weak pull-up. Enabled in RCIO,
INTIO2 and ECIO modes only.
IOCA4
1
I
TTL Interrupt-on-pin change
AN3
1
I ANA A/D input channel 3. Default configuration on POR.
OSC2
x
O ANA Main oscillator feedback output connection (XT, HS and LP modes).
CLKOUT
x
O DIG System cycle clock output (FOSC/4) in RC, INTIO1 and EC Oscillator
modes.
RA5/IOCA5/OSC1/
CLKIN
RA5
0
O DIG LATA<5> data output. Disabled in external oscillator modes.
1
I
TTL PORTA<5> data input. Disabled in external oscillator modes; Program-
mable weak pull-up.
IOCA5
1
I
TTL Interrupt-on-pin change
OSC1
x
I ANA Main oscillator input connection.
CLKIN
x
I ANA Main clock input connection.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: RA0 and RA1 do not have corresponding TRISA bits. In Port mode, these pins are input only. USB data direction is
determined by the USB configuration.
2: RA3 does not have a corresponding TRISA bit. This pin is always an input regardless of mode.
 2010 Microchip Technology Inc.
Preliminary
DS41350E-page 87