PIC18F-LF1XK50 Datasheet, PDF (120/420 Pages) Microchip Technology – 20-Pin USB Flash Microcontrollers

PIC18F/LF1XK50
14.3 Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCP1
pin can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high)
• remain unchanged (that is, reflects the state of the
I/O latch)
The action on the pin is based on the value of the mode
select bits (CCP1M<3:0>). At the same time, the inter-
rupt flag bit, CCP1IF, is set.
14.3.1 CCP PIN CONFIGURATION
The user must configure the CCP1 pin as an output by
clearing the appropriate TRIS bit.
Note:
Clearing the CCP1CON register will force
the CCP1 compare output latch (depend-
ing on device configuration) to the default
low level. This is not the PORTC I/O data
latch.
14.3.2 TIMER1/TIMER3 MODE SELECTION
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation will not work reliably.
14.3.3 SOFTWARE INTERRUPT MODE
When the Generate Software Interrupt mode is chosen
(CCP1M<3:0> = 1010), the CCP1 pin is not affected.
Only the CCP1IF interrupt flag is affected.
14.3.4 SPECIAL EVENT TRIGGER
The CCP module is equipped with a Special Event Trig-
ger. This is an internal hardware signal generated in
Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the Compare Special Event Trigger mode
(CCP1M<3:0> = 1011).
The Special Event Trigger resets the timer register pair
for whichever timer resource is currently assigned as the
module’s time base. This allows the CCPR1 registers to
serve as a programmable period register for either timer.
The Special Event Trigger can also start an A/D conver-
sion. In order to do this, the A/D converter must already
be enabled.
FIGURE 14-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
0
TMR1H TMR1L
1
TMR3H
T3CCP1
TMR3L
Comparator
Compare
Match
CCPR1H CCPR1L
Special Event Trigger
(Timer1/Timer3 Reset, A/D Trigger)
Set CCP1IF
Output
Logic
4
CCP1CON<3:0>
SQ
R
CCP1 pin
TRIS
Output Enable
DS41350E-page 120
Preliminary
 2010 Microchip Technology Inc.