PIC18F-LF1XK50 Datasheet, PDF (274/420 Pages) Microchip Technology – 20-Pin USB Flash Microcontrollers

PIC18F/LF1XK50
22.7 Oscillator
The USB module has specific clock requirements. For
full-speed operation, the clock source must be 48 MHz.
Even so, the microcontroller core and other peripherals
are not required to run at that clock speed. Available
clocking options are described in detail in Section 2.11
“USB Operation”.
22.8 Interrupt-On-Change for D+/D-
pins
The PIC18F/LF1XK50 has interrupt-on-change func-
tionality on both D+ and D- data pins. This feature
allows the device to detect voltage level changes
when first connected to a USB host/hub.
The USB host/hub has 15K pull-down resistors on the D+
and D- pins. When the PIC18F/LF1XK50 attaches to the
bus the D+ and D- pins can detect voltage changes.
External resistors are needed for each pin to maintain a
high state on the pins when detached.
The USB module must be disable (USBEN = 0) for the
interrupt-on-change to function. Enabling the USB
module (USBEN = 1) will automatically disable the
interrupt-on-change for D+ and D- pins. Refer to
Section 7.11 “PORTA and PORTB Inter-
rupt-on-Change” for mode detail.
22.9 USB Firmware and Drivers
Microchip provides a number of application-specific
resources, such as USB firmware and driver support.
Refer to www.microchip.com for the latest firmware and
driver support.
TABLE 22-4: REGISTERS ASSOCIATED WITH USB MODULE OPERATION⁽¹⁾
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Details on
Page:
INTCON
IPR2
PIR2
PIE2
UCON
UCFG
USTAT
UADDR
UFRML
UFRMH
UIR
UIE
UEIR
UEIE
UEP0
UEP1
UEP2
UEP3
UEP4
UEP5
UEP6
UEP7
Legend:
Note 1:
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RABIE
TMR0IF
INT0IF
RABIF
70
OSCFIP
C1IP
C2IP
EEIP
BCL1IP
USBIP
TMR3IP
—
78
OSCFIF
C1IF
C2IF
EEIF
BCL1IF
USBIF
TMR3IF
—
74
OSCFIE
C1IE
C2IE
EEIE
BCL1IE
USBIE
TMR3IE
—
76
—
PPBRST
SE0
PKTDIS USBEN RESUME SUSPND
—
252
UTEYE
—
—
UPUEN
—
FSEN
PPB1
PPB0
254
—
ENDP3 ENDP2 ENDP1 ENDP0
DIR
PPBI
—
256
—
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
258
FRM7
FRM6
FRM5
FRM4
FRM3
FRM2
FRM1
FRM0
252
—
—
—
—
—
FRM10
FRM9
FRM8
252
—
SOFIF STALLIF IDLEIF
TRNIF
ACTVIF UERRIF URSTIF
266
—
SOFIE STALLIE IDLEIE
TRNIE
ACTVIE UERRIE URSTIE
268
BTSEF
—
—
BTOEF DFN8EF CRC16EF CRC5EF PIDEF
269
BTSEE
—
—
BTOEE DFN8EE CRC16EE CRC5EE PIDEE
270
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
257
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
257
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
257
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
257
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
257
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
257
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
257
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
257
— = unimplemented, read as ‘0’. Shaded cells are not used by the USB module.
This table includes only those hardware mapped SFRs located in Bank 15 of the data memory space. The Buffer
Descriptor registers, which are mapped into Bank 4 and are not true SFRs, are listed separately in Table 22-3.
DS41350E-page 274
Preliminary
 2010 Microchip Technology Inc.