PIC18F-LF1XK50 Datasheet, PDF (297/420 Pages) Microchip Technology – 20-Pin USB Flash Microcontrollers

PIC18F/LF1XK50
REGISTER 24-5: CONFIG3H: CONFIGURATION REGISTER 3 HIGH
R/P-1
U-0
U-0
U-0
R/P-1
U-0
U-0
U-0
MCLRE
—
—
—
HFOFST
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
bit 7
bit 6-4
bit 3
bit 2-0
MCLRE: MCLR Pin Enable bit
1 = MCLR pin enabled; RA3 input pin disabled
0 = RA3 input pin enabled; MCLR disabled
Unimplemented: Read as ‘0’
HFOFST: HFINTOSC Fast Start-up bit
1 = HFINTOSC starts clocking the CPU without waiting for the oscillator to stabilize.
0 = The system clock is held off until the HFINTOSC is stable.
Unimplemented: Read as ‘0’
REGISTER 24-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW
R/W-1⁽¹⁾
R/W-0
U-0
BKBUG
ENHCPU
—
bit 7
U-0
R/P-0
R/P-1
U-0
—
BBSIZ
LVP
—
R/P-1
STVREN
bit 0
Legend:
R = Readable bit
P = Programmable bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
bit 7
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
BKBUG: Background Debugger Enable bit⁽¹⁾
1 = Background debugger disabled
0 = Background debugger functions enabled
ENHCPU: Enhanced CPU Enable bit
1 = Enhanced CPU enabled
0 = Enhanced CPU disabled
Unimplemented: Read as ‘0’
BBSIZ: Boot BLock Size Select bit
1 = 2 kW boot block size for PIC18F14K50/PIC18LF14K50 (1 kW boot block size for
PIC18F13K50/PIC18LF13K50)
0 = 1 kW boot block size for PIC18F14K50/PIC18LF14K50 (512 W boot block size for
PIC18F13K50/PIC18LF13K50)
LVP: Single-Supply ICSP™ Enable bit
1 = Single-Supply ICSP enabled
0 = Single-Supply ICSP disabled
Unimplemented: Read as ‘0’
STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack full/underflow will cause Reset
0 = Stack full/underflow will not cause Reset
Note 1: BKBUG is only used for the ICD device. Otherwise, this bit is unimplemented and reads as ‘1’.
 2010 Microchip Technology Inc.
Preliminary
DS41350E-page 297