PIC18F-LF1XK50 Datasheet, PDF (147/420 Pages) Microchip Technology – 20-Pin USB Flash Microcontrollers

15.2.8 OPERATION IN POWER-MANAGED
MODES
In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode; in
the case of the Sleep mode, all clocks are halted.
In all Idle modes, a clock is provided to the peripherals.
That clock could be from the primary clock source, the
secondary clock (Timer1 oscillator at 32.768 kHz) or
the INTOSC source. See Section 19.0 “Power-Man-
aged Modes” for additional information.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
When MSSP interrupts are enabled, after the master
completes sending data, an MSSP interrupt will wake
the controller:
• from Sleep, in slave mode
• from Idle, in slave or master mode
If an exit from Sleep or Idle mode is not desired, MSSP
interrupts should be disabled.
In SPI master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the devices
wakes. After the device returns to RUN mode, the mod-
ule will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI
PIC18F/LF1XK50
Transmit/Receive Shift register. When all 8 bits have
been received, the MSSP interrupt flag bit will be set
and if enabled, will wake the device.
15.2.9 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
15.2.10 BUS MODE COMPATIBILITY
Table 15-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 15-1: SPI BUS MODES
Standard SPI Mode
Terminology
Control Bits State
CKP
CKE
0, 0
0
1
0, 1
0
0
1, 0
1
1
1, 1
1
0
There is also an SMP bit which controls when the data
is sampled.
TABLE 15-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE
PIR1
—
ADIF
RCIF
TXIF
SSPIF
PIE1
—
ADIE
RCIE
TXIE SSPIE
IPR1
—
ADIP
RCIP
TXIP SSPIP
TRISB
TRISB7 TRISB6 TRISB5 TRISB4
—
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3
SSPBUF SSP Receive Buffer/Transmit Register
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3
SSPSTAT
SMP
CKE
D/A
P
S
Legend: Shaded cells are not used by the MSSP in SPI mode.
TMR0IF
CCP1IF
CCP1IE
CCP1IP
—
TRISC2
SSPM2
R/W
Bit 1
INT0IF
TMR2IF
TMR2IE
TMR2IP
—
TRISC1
SSPM1
UA
Bit 0
RABIF
TMR1IF
TMR1IE
TMR1IP
—
TRISC0
SSPM0
BF
Reset
Values
on page
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 2010 Microchip Technology Inc.
Preliminary
DS41350E-page 147