PIC18F-LF1XK50 Datasheet, PDF (415/420 Pages) Microchip Technology – 20-Pin USB Flash Microcontrollers

PIC18F/LF1XK50
I2C Bus Start/Stop Bits ............................................ 394
SPI Mode ................................................................. 393
Top-of-Stack Access .......................................................... 30
TRISA Register .................................................................. 85
TRISB Register ............................................................ 90, 94
TSTFSZ ........................................................................... 349
Two-Speed Start-up ......................................................... 291
Two-Word Instructions
Example Cases .......................................................... 34
TXREG ............................................................................. 183
TXSTA Register ............................................................... 190
BRGH Bit ................................................................. 193
U
Universal Serial Bus
Address Register (UADDR) ..................................... 258
Associated Registers ............................................... 274
Buffer Descriptor Table ............................................ 259
Buffer Descriptors .................................................... 259
Address Validation ........................................... 262
Assignment in Different Buffering Modes ........ 264
BDnSTAT Register (CPU Mode) ..................... 260
BDnSTAT Register (SIE Mode) ....................... 262
Byte Count ....................................................... 262
Example ........................................................... 259
Memory Map .................................................... 263
Ownership ........................................................ 259
Ping-Pong Buffering ......................................... 263
Register Summary ........................................... 264
Status and Configuration ................................. 259
Class Specifications and Drivers ............................. 276
Descriptors ............................................................... 276
Endpoint Control ...................................................... 257
Enumeration ............................................................. 276
External Pull-up Resistors ........................................ 255
Eye Pattern Test Enable .......................................... 255
Firmware and Drivers ............................................... 274
Frame Number Registers ......................................... 258
Frames ..................................................................... 275
Internal Pull-up Resistors ......................................... 255
Internal Transceiver ................................................. 253
Interrupts .................................................................. 265
and USB Transactions ..................................... 265
Layered Framework ................................................. 275
Oscillator Requirements ........................................... 274
Overview .......................................................... 251, 275
Ping-Pong Buffer Configuration ............................... 255
Power ....................................................................... 275
Power Modes ........................................................... 271
Bus Power Only ............................................... 271
Dual Power with Self-Power Dominance ......... 272
Self-Power Only ............................................... 271
RAM ......................................................................... 258
Memory Map .................................................... 258
Speed ....................................................................... 276
Status and Control ................................................... 252
Transfer Types ......................................................... 275
UFRMH:UFRML Registers ...................................... 258
USART
Synchronous Master Mode
Requirements, Synchronous Receive ............. 390
Requirements, Synchronous Transmission ..... 390
Timing Diagram, Synchronous Receive .......... 390
Timing Diagram, Synchronous Transmission .. 390
USB Module Electrical Specifications .............................. 376
USB RAM
Serial Interface Engine (SIE) ..................................... 35
USB. See Universal Serial Bus.
V
Voltage Reference (VR)
Specifications .......................................................... 389
Voltage Reference. See Comparator Voltage Reference
(CVREF)
Voltage References
Fixed Voltage Reference (FVR) .............................. 246
VR Stabilization ....................................................... 246
VREF. SEE ADC Reference Voltage
W
Wake-up on Break ........................................................... 198
Watchdog Timer (WDT) ........................................... 291, 302
Associated Registers ............................................... 303
Control Register ....................................................... 303
Programming Considerations .................................. 302
Specifications .......................................................... 385
WCOL ...................................................... 169, 170, 171, 174
WCOL Status Flag ................................... 169, 170, 171, 174
WDTCON Register .......................................................... 303
WPUA Register .................................................................. 86
WPUB Register .................................................................. 91
WWW Address ................................................................ 417
WWW, On-Line Support ...................................................... 7
X
XORLW ........................................................................... 349
XORWF ........................................................................... 350
 2010 Microchip Technology Inc.
Preliminary
DS41350E-page 415