PIC18F-LF1XK50 Datasheet, PDF (23/420 Pages) Microchip Technology – 20-Pin USB Flash Microcontrollers

PIC18F/LF1XK50
2.7 Oscillator Start-up Timer
The Primary External Oscillator, when configured for
LP, XT or HS modes, incorporates an Oscillator Start-up
Timer (OST). The OST ensures that the oscillator starts
and provides a stable clock to the oscillator module.
The OST times out when 1024 oscillations on OSC1
have occurred. During the OST period, with the system
clock set to the Primary External Oscillator, the program
counter does not increment suspending program
execution. The OST period will occur following:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Wake-up from Sleep
• Oscillator being enabled
• Expiration of Power-up Timer (PWRT)
In order to minimize latency between external oscillator
start-up and code execution, the Two-Speed Start-up
mode can be selected. See Section 2.12 “Two-Speed
Start-up Mode” for more information.
2.8 Clock Switching
The device contains circuitry to prevent clock “glitches”
due to a change of the system clock source. To
accomplish this, a short pause in the system clock
occurs during the clock switch. If the new clock source
is not stable (e.g., OST is active), the device will
continue to execute from the old clock source until the
new clock source becomes stable. The timing of a
clock switch is as follows:
1. SCS<1:0> bits of the OSCCON register are
modified.
2. The system clock will continue to operate from
the old clock until the new clock is ready.
3. Clock switch circuitry waits for two consecutive
rising edges of the old clock after the new clock
is ready.
4. The system clock is held low, starting at the next
falling edge of the old clock.
5. Clock switch circuitry waits for an additional two
rising edges of the new clock.
6. On the next falling edge of the new clock, the
low hold on the system clock is release and the
new clock is switched in as the system clock.
7. Clock switch is complete.
Refer to Figure 2-5 for more details.
FIGURE 2-5:
CLOCK SWITCH TIMING
High Speed Low Speed
Old Clock
Start-up Time⁽¹⁾
New Clock
New Clk Ready
IRCF <2:0> ^{Select Old}
Select New
System Clock
Clock Sync
Running
Low Speed High Speed
Old Clock
Start-up Time⁽¹⁾
New Clock
New Clk Ready
IRCF <2:0> Select Old
Select New
System Clock
Clock Sync
Running
Note 1: Start-up time includes TOST (1024 TOSC) for external clocks, plus TPLL (approx. 2 ms) for HSPLL mode.
 2010 Microchip Technology Inc.
Preliminary
DS41350E-page 23