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PIC18F-LF1XK50 Datasheet, PDF (242/420 Pages) Microchip Technology – 20-Pin USB Flash Microcontrollers | |||
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PIC18F/LF1XK50
TABLE 20-2: SRCLK FREQUENCY TABLE
SRCLK
Divider FOSC = 20 MHz FOSC = 16 MHz FOSC = 8 MHz FOSC = 4 MHz
111
512
110
256
101
128
100
64
011
32
010
16
001
8
000
4
25.6 ïs
12.8 ïs
6.4 ïs
3.2 ïs
1.6 ïs
0.8 ïs
0.4 ïs
0.2 ïs
32 ïs
16 ïs
8 ïs
4 ïs
2 ïs
1 ïs
0.5 ïs
0.25 ïs
64 ïs
32 ïs
16 ïs
8 ïs
4 ïs
2 ïs
1 ïs
0.5 ïs
128 ïs
64 ïs
32 ïs
16 ïs
8 ïs
4 ïs
2 ïs
1 ïs
FOSC = 1 MHz
512 ïs
256 ïs
128 ïs
64 ïs
32 ïs
16 ïs
8 ïs
4 ïs
REGISTER 20-1: SRCON0: SR LATCH CONTROL REGISTER
R/W-0
SRLEN
bit 7
R/W-0
SRCLK2
R/W-0
SRCLK1
R/W-0
SRCLK0
R/W-0
SRQEN
R/W-0
SRNQEN
R/W-0
SRPS
R/W-0
SRPR
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
â1â = Bit is set
U = Unimplemented
â0â = Bit is cleared
C = Clearable only bit
x = Bit is unknown
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
Note 1:
SRLEN: SR Latch Enable bit(1)
1 = SR latch is enabled
0 = SR latch is disabled
SRCLK<2:0>(1): SR Latch Clock divider bits
000 = 1/4 Peripheral cycle clock
001 = 1/8 Peripheral cycle clock
010 = 1/16 Peripheral cycle clock
011 = 1/32 Peripheral cycle clock
100 = 1/64 Peripheral cycle clock
101 = 1/128 Peripheral cycle clock
110 = 1/256 Peripheral cycle clock
111 = 1/512 Peripheral cycle clock
SRQEN: SR Latch Q Output Enable bit
If SRNQEN = 0
1 = Q is present on the RC4 pin
0 = Q is internal only
SRNQEN: SR Latch Q Output Enable bit
1 = Q is present on the RC4 pin
0 = Q is internal only
SRPS: Pulse Set Input of the SR Latch
1 = Pulse input
0 = Always reads back â0â
SRPR: Pulse Reset Input of the SR Latch
1 = Pulse input
0 = Always reads back â0â
Changing the SRCLK bits while the SR latch is enabled may cause false triggers to the set and Reset
inputs of the latch.
DS41350E-page 242
Preliminary
ï£ 2010 Microchip Technology Inc.
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