PIC18F-LF1XK50 Datasheet, PDF (43/420 Pages) Microchip Technology – 20-Pin USB Flash Microcontrollers

PIC18F1XK50/PIC18LF1XK50
TABLE 3-2: REGISTER FILE SUMMARY (PIC18F/LF1XK50) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on
page:
SPBRGH EUSART Baud Rate Generator Register, High Byte
0000 0000 287, 181
SPBRG EUSART Baud Rate Generator Register, Low Byte
0000 0000 287, 181
RCREG EUSART Receive Register
0000 0000 287, 182
TXREG
EUSART Transmit Register
0000 0000 287, 181
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D 0000 0010 287, 190
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x 287, 191
EEADR
EEADR7 EEADR6 EEADR5 EEADR4
EEADR3
EEADR2
EEADR1
EEADR0 0000 0000 287, 52,
61
EEDATA EEPROM Data Register
0000 0000 287, 52,
61
EECON2 EEPROM Control Register 2 (not a physical register)
0000 0000 287, 52,
61
EECON1
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
xx-0 x000 287, 53,
61
IPR2
OSCFIP
C1IP
C2IP
EEIP
BCLIP
USBIP
TMR3IP
–
1111 111- 288, 78
PIR2
OSCFIF
C1IF
C2IF
EEIF
BCLIF
USBIF
TMR3IF
–
0000 000- 288, 74
PIE2
OSCFIE
C1IE
C2IE
EEIE
BCLIE
USBIE
TMR3IE
–
0000 000- 288, 76
IPR1
–
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP ^{-111 1111 288, 77}
PIR1
–
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF ^{-000 0000 288, 73}
PIE1
–
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE ^{-000 0000 288, 75}
OSCTUNE INTSRC SPLLEN
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0 0000 0000 22, 288
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0 ^{1111 1111 288, 94}
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
–
–
–
–
1111 ---- 288, 89
TRISA
–
–
TRISA5
TRISA4
–
–
–
–
--11 ---- 288, 83
LATC
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0 ^{xxxx xxxx 288, 94}
LATB
LATB7
LATB6
LATB5
LATB4
–
–
–
–
xxxx ---- 288, 89
LATA
–
–
LATA5
LATA4
–
–
–
–
--xx ---- 288, 83
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0 xxxx xxxx 288, 94
PORTB
RB7
RB6
RB5
RB4
–
–
–
–
xxxx ---- 288, 89
PORTA
–
–
RA5
RA4
RA3⁽²⁾
–
RA1⁽³⁾
RA0^{(3) --xx x-xx 288, 83}
ANSELH
—
—
—
—
ANS11
ANS10
ANS9
ANS8 ---- 1111 288, 99
ANSEL
ANS7
ANS6
ANS5
ANS4
ANS3
—
—
—
1111 1--- 288, 98
IOCB
IOCB7
IOCB6
IOCB5
IOCB4
—
—
—
—
0000 ---- 288, 89
IOCA
—
—
IOCA5
IOCA4
IOCA3
—
IOCA1
IOCA0 --00 0-00 288, 83
WPUB
WPUB7
WPUB6
WPUB5
WPUB4
—
—
—
—
1111 ---- 288, 89
WPUA
—
—
WPUA5
WPUA4
WPUA3
—
—
—
--11 1--- 285, 89
SLRCON
—
—
—
—
—
SLRC
SLRB
SLRA ---- -111 288, 100
SSPMSK
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0 1111 1111 288, 154
CM1CON0
C1ON
C1OUT
C1OE
C1POL
C1SP
C1R
C1CH1
C1CH0 0000 1000 288, 229
CM2CON1 ^{MC1OUT MC2OUT C1RSEL C2RSEL}
C1HYS
C2HYS
C1SYNC C2SYNC 0000 0000 288, 230
CM2CON0
C2ON
C2OUT
C2OE
C2POL
C2SP
C2R
C2CH1
C2CH0 0000 1000 288, 230
SRCON1
SRSPE SRSCKE SRSC2E SRSC1E
SRRPE
SRRCKE SRRC2E SRRC1E 0000 0000 288, 243
SRCON0
SRLEN
SRCLK2 SRCLK1 SRCLK0
SRQEN
SRNQEN
SRPS
SRPR 0000 0000 288, 242
UCON
—
PPBRST
SE0
PKTDIS
USBEN
RESUME SUSPND
—
-0x0 000- 288, 252
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 23.4 “Brown-out Reset (BOR)”.
The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit is
read-only.
Bits RA0 and RA1 are available only when USB is disabled.
 2010 Microchip Technology Inc.
Preliminary
DS41350E-page 43