PIC18F-LF1XK50 Datasheet, PDF (42/420 Pages) Microchip Technology – 20-Pin USB Flash Microcontrollers

PIC18F1XK50/PIC18LF1XK50
TABLE 3-2: REGISTER FILE SUMMARY (PIC18F/LF1XK50) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on
page:
TMR0H Timer0 Register, High Byte
TMR0L
Timer0 Register, Low Byte
T0CON
TMR0ON T08BIT
OSCCON
IDLEN
IRCF2
OSCCON2
—
—
WDTCON
—
—
RCON
IPEN
SBOREN⁽¹⁾
T0CS
IRCF1
—
—
—
TMR1H
TMR1L
Timer1 Register, High Byte
Timer1 Register, Low Bytes
T0SE
IRCF0
—
—
RI
PSA
OSTS
—
—
TO
T0PS2
IOSF
PRI_SD
—
PD
T0PS1
SCS1
HFIOFL
—
POR
0000 0000 286, 103
xxxx xxxx 286, 103
T0PS0 1111 1111 286, 101
SCS0 0011 qq00 286, 20
LFIOFS ---- -10x 286, 21
SWDTEN --- ---0 286, 303
BOR
0q-1 11q0 277,
284, 79
xxxx xxxx 286, 110
xxxx xxxx 286, 110
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
RD16
T1RUN T1CKPS1 T1CKPS0
Timer2 Register
Timer2 Period Register
—
T2OUTPS3 T2OUTPS2 T2OUTPS1
SSP Receive Buffer/Transmit Register
T1OSCEN
T2OUTPS0
T1SYNC
TMR2ON
TMR1CS
T2CKPS1
SSP Address Register in I²C™ Slave Mode. SSP Baud Rate Reload Register in I²C Master Mode.
TMR1ON 0000 0000 286, 105
0000 0000 286, 112
1111 1111 286, 112
T2CKPS0 -000 0000 286, 111
xxxx xxxx 286,
143, 144
0000 0000 286, 144
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 286,
137, 146
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0 0000 0000 286,
137, 146
SSPCON2
GCEN ACKSTAT ACKDT
ACKEN
RCEN
PEN
RSEN
SEN 0000 0000 286, 147
ADRESH A/D Result Register, High Byte
xxxx xxxx 287, 221
ADRESL A/D Result Register, Low Byte
xxxx xxxx 287, 221
ADCON0
—
—
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON --00 0000 287, 215
ADCON1
—
—
—
—
PVCFG1
PVCFG0
NVCFG1 NVCFG0 ^{---- 0000 287, 216}
ADCON2
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0 0-00 0000 287, 217
CCPR1H Capture/Compare/PWM Register 1, High Byte
xxxx xxxx 287, 138
CCPR1L Capture/Compare/PWM Register 1, Low Byte
xxxx xxxx 287, 138
CCP1CON
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1 CCP1M0 0000 0000 287, 117
REFCON2
—
—
—
DAC1R4
DAC1R3
DAC1R2
DAC1R1 DAC1R0 ---0 0000 287, 248
REFCON1
D1EN
D1LPS
DAC1OE
---
D1PSS1
D1PSS0
—
D1NSS 000- 00-0 287, 248
REFCON0 ^{FVR1EN FVR1ST FVR1S1 FVR1S0}
—
—
—
—
0001 00-- 287, 247
PSTRCON
—
—
—
STRSYNC
STRD
STRC
STRB
STRA ---0 0001 287, 134
BAUDCON ABDOVF
RCIDL
DTRXP
CKTXP
BRG16
—
WUE
ABDEN 0100 0-00 287, 192
PWM1CON PRSEN
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0 0000 0000 287, 133
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1
PSSAC0
PSSBD1 PSSBD0 0000 0000 287, 129
TMR3H Timer3 Register, High Byte
xxxx xxxx 287, 115
TMR3L
Timer3 Register, Low Byte
xxxx xxxx 287, 115
T3CON
RD16
—
T3CKPS1 T3CKPS0 T3CCP1
T3SYNC
TMR3CS TMR3ON 0-00 0000 287, 113
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 23.4 “Brown-out Reset (BOR)”.
The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit is
read-only.
Bits RA0 and RA1 are available only when USB is disabled.
DS41350E-page 42
Preliminary
 2010 Microchip Technology Inc.